1ebcd5d51SShengjiu Wang /* SPDX-License-Identifier: GPL-2.0-only */ 2ebcd5d51SShengjiu Wang /* 3ebcd5d51SShengjiu Wang * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> 4ebcd5d51SShengjiu Wang * Copyright 2021 NXP 5ebcd5d51SShengjiu Wang */ 6ebcd5d51SShengjiu Wang 7ebcd5d51SShengjiu Wang #ifndef _IMX_RPROC_H 8ebcd5d51SShengjiu Wang #define _IMX_RPROC_H 9ebcd5d51SShengjiu Wang 10ebcd5d51SShengjiu Wang /* address translation table */ 11ebcd5d51SShengjiu Wang struct imx_rproc_att { 12ebcd5d51SShengjiu Wang u32 da; /* device address (From Cortex M4 view)*/ 13ebcd5d51SShengjiu Wang u32 sa; /* system bus address */ 14ebcd5d51SShengjiu Wang u32 size; /* size of reg range */ 15ebcd5d51SShengjiu Wang int flags; 16ebcd5d51SShengjiu Wang }; 17ebcd5d51SShengjiu Wang 18ebcd5d51SShengjiu Wang /* Remote core start/stop method */ 19ebcd5d51SShengjiu Wang enum imx_rproc_method { 20ebcd5d51SShengjiu Wang IMX_RPROC_NONE, 21ebcd5d51SShengjiu Wang /* Through syscon regmap */ 22ebcd5d51SShengjiu Wang IMX_RPROC_MMIO, 23ebcd5d51SShengjiu Wang /* Through ARM SMCCC */ 24ebcd5d51SShengjiu Wang IMX_RPROC_SMC, 25d2320a04SShengjiu Wang /* Through System Control Unit API */ 26d2320a04SShengjiu Wang IMX_RPROC_SCU_API, 27ebcd5d51SShengjiu Wang }; 28ebcd5d51SShengjiu Wang 29ebcd5d51SShengjiu Wang struct imx_rproc_dcfg { 30ebcd5d51SShengjiu Wang u32 src_reg; 31ebcd5d51SShengjiu Wang u32 src_mask; 32ebcd5d51SShengjiu Wang u32 src_start; 33ebcd5d51SShengjiu Wang u32 src_stop; 34*49f80a7aSMarek Vasut u32 gpr_reg; 35*49f80a7aSMarek Vasut u32 gpr_wait; 36ebcd5d51SShengjiu Wang const struct imx_rproc_att *att; 37ebcd5d51SShengjiu Wang size_t att_size; 38ebcd5d51SShengjiu Wang enum imx_rproc_method method; 39ebcd5d51SShengjiu Wang }; 40ebcd5d51SShengjiu Wang 41ebcd5d51SShengjiu Wang #endif /* _IMX_RPROC_H */ 42