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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dgen2_engine_cs.c1 // SPDX-License-Identifier: MIT
19 u32 cmd, *cs; in gen2_emit_flush() local
25 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
26 if (IS_ERR(cs)) in gen2_emit_flush()
27 return PTR_ERR(cs); in gen2_emit_flush()
29 *cs++ = cmd; in gen2_emit_flush()
30 while (num_store_dw--) { in gen2_emit_flush()
31 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
32 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
33 *cs++ = 0; in gen2_emit_flush()
[all …]
H A Dgen7_renderclear.c1 // SPDX-License-Identifier: MIT
12 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
48 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
52 return bv->max_threads; in num_primitives()
59 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
62 bv->max_threads = 70; in batch_get_defaults()
64 case 2: in batch_get_defaults()
65 bv->max_threads = 140; in batch_get_defaults()
68 bv->max_threads = 280; in batch_get_defaults()
71 bv->surface_height = 16 * 16; in batch_get_defaults()
[all …]
H A Dintel_migrate.c1 // SPDX-License-Identifier: MIT
33 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
48 vm->insert_page(vm, 0, d->offset, in xehpsdv_toggle_pdes()
49 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_toggle_pdes()
51 GEM_BUG_ON(!pt->is_compact); in xehpsdv_toggle_pdes()
52 d->offset += SZ_2M; in xehpsdv_toggle_pdes()
68 vm->insert_page(vm, px_dma(pt), d->offset, in xehpsdv_insert_pte()
69 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_insert_pte()
71 d->offset += SZ_64K; in xehpsdv_insert_pte()
80 vm->insert_page(vm, px_dma(pt), d->offset, in insert_pte()
[all …]
H A Dselftest_lrc.c1 // SPDX-License-Identifier: MIT
26 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
28 #define NUM_GPR_DW (NUM_GPR * 2) /* each GPR is 2 dwords */
35 return __vm_create_scratch_for_read_pinned(&gt->ggtt->vm, PAGE_SIZE); in create_scratch()
57 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
68 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
72 return -ETIME; in wait_for_submit()
81 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
84 u32 *cs; in emit_semaphore_signal() local
90 cs = intel_ring_begin(rq, 4); in emit_semaphore_signal()
[all …]
H A Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
25 return *a - *b; in cmp_u64()
31 return (a[1] + 2 * a[2] + a[3]) >> 2; in trifilter()
34 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
36 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
40 *cs++ = value; in emit_wait()
41 *cs++ = offset; in emit_wait()
42 *cs++ = 0; in emit_wait()
44 return cs; in emit_wait()
47 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
[all …]
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
20 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
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/openbmc/qemu/target/loongarch/kvm/
H A Dkvm.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #include "qemu/error-report.h"
15 #include "qemu/main-loop.h"
21 #include "exec/address-spaces.h"
27 #include "cpu-csr.h"
37 static int kvm_get_stealtime(CPUState *cs) in kvm_get_stealtime() argument
39 CPULoongArchState *env = cpu_env(cs); in kvm_get_stealtime()
44 .addr = (uint64_t)&env->stealtime.guest_addr, in kvm_get_stealtime()
47 err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); in kvm_get_stealtime()
52 err = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, attr); in kvm_get_stealtime()
[all …]
/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
78 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
79 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
80 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
81 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
82 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
83 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
84 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
85 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c1 // SPDX-License-Identifier: GPL-2.0
46 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
59 * Args: freq - current sequence frequency
60 * dram_info - main struct
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
70 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
103 * Read results to arrays - Results are required for WL in ddr3_write_leveling_hw()
[all …]
H A Dddr3_read_leveling.c1 // SPDX-License-Identifier: GPL-2.0
44 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
48 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
56 * Args: dram_info - main struct
57 * freq - current sequence frequency
65 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
73 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
[all …]
H A Dddr3_spd.c1 // SPDX-License-Identifier: GPL-2.0
28 #define SPD_DEV_TYPE_BYTE 2
33 #define SPD_MODULE_TYPE_UDIMM 2
169 u32 min_write_recovery_time; /* DDR3/2 only */
170 u32 min_write_to_read_cmd_delay; /* DDR3/2 only */
171 u32 min_read_to_prech_cmd_delay; /* DDR3/2 only */
173 u32 min_refresh_recovery; /* DDR3/2 only */
196 * Name: ddr3_get_dimm_num - Find number of dimms and their addresses
198 * Args: dimm_addr - array of dimm addresses
211 dimm_cur_addr--) { in ddr3_get_dimm_num()
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
20 #define MCF_BUSCLK (MCF_CLK / 2)
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
H A Dm5407sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
20 #define MCF_BUSCLK (MCF_CLK / 2)
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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/openbmc/qemu/target/openrisc/
H A Dcpu.c22 #include "qemu/qemu-print.h"
24 #include "exec/exec-all.h"
25 #include "fpu/softfloat-helpers.h"
28 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) in openrisc_cpu_set_pc() argument
30 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_set_pc()
32 cpu->env.pc = value; in openrisc_cpu_set_pc()
33 cpu->env.dflag = 0; in openrisc_cpu_set_pc()
36 static vaddr openrisc_cpu_get_pc(CPUState *cs) in openrisc_cpu_get_pc() argument
38 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_get_pc()
40 return cpu->env.pc; in openrisc_cpu_get_pc()
[all …]
/openbmc/qemu/target/m68k/
H A Dm68k-semi.c4 * Copyright (c) 2005-2007 CodeSourcery.
8 * the Free Software Foundation; either version 2 of the License, or
21 * https://sourceware.org/git/?p=newlib-cygwin.git;a=blob;f=libgloss/m68k/m68k-semi.txt;hb=HEAD
36 #define HOSTED_OPEN 2
78 static void m68k_semi_u32_cb(CPUState *cs, uint64_t ret, int err) in m68k_semi_u32_cb() argument
80 CPUM68KState *env = cpu_env(cs); in m68k_semi_u32_cb()
82 target_ulong args = env->dregs[1]; in m68k_semi_u32_cb()
90 qemu_log_mask(LOG_GUEST_ERROR, "m68k-semihosting: return value " in m68k_semi_u32_cb()
95 static void m68k_semi_u64_cb(CPUState *cs, uint64_t ret, int err) in m68k_semi_u64_cb() argument
97 CPUM68KState *env = cpu_env(cs); in m68k_semi_u64_cb()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_cmd.c1 // SPDX-License-Identifier: MIT
23 static u32 *pxp_emit_session_selection(u32 *cs, u32 idx) in pxp_emit_session_selection() argument
25 *cs++ = MFX_WAIT_PXP; in pxp_emit_session_selection()
28 *cs++ = MI_FLUSH_DW; in pxp_emit_session_selection()
29 *cs++ = 0; in pxp_emit_session_selection()
30 *cs++ = 0; in pxp_emit_session_selection()
33 *cs++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx); in pxp_emit_session_selection()
35 *cs++ = MFX_WAIT_PXP; in pxp_emit_session_selection()
38 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_PROTECTED_MEM_EN | in pxp_emit_session_selection()
40 *cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT; in pxp_emit_session_selection()
[all …]
/openbmc/qemu/semihosting/
H A Darm-compat-semi.c3 * semihosting syscalls design. This includes Arm and RISC-V processors
10 * Adapted for systems other than ARM, including RISC-V, by Keith Packard
14 * the Free Software Foundation; either version 2 of the License, or
27 * https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst
29 * RISC-V Semihosting is documented in:
30 * RISC-V Semihosting
31 * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
40 #include "semihosting/common-semi.h"
130 if (!mr->ram || mr->readonly) { in find_ram_cb()
134 if (size > info->ramsize) { in find_ram_cb()
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/openbmc/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
16 * regs has the to-be-set values for DDR controller registers
20 * 2 resumes from step 1 and continues to initialize
36 int csn = -1; in fsl_ddr_set_memctl_regs()
51 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) in fsl_ddr_set_memctl_regs()
52 case 2: in fsl_ddr_set_memctl_regs()
66 if (step == 2) in fsl_ddr_set_memctl_regs()
69 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
70 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
[all …]
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c7 * This code is licensed under the GPL, version 2 or (at your option)
18 #include "qemu/main-loop.h"
24 #include "target/arm/cpu-features.h"
36 return env->gicv3state; in icc_cs_from_env()
50 static inline int icv_min_vbpr(GICv3CPUState *cs) in icv_min_vbpr() argument
52 return 7 - cs->vprebits; in icv_min_vbpr()
55 static inline int ich_num_aprs(GICv3CPUState *cs) in ich_num_aprs() argument
57 /* Return the number of virtual APR registers (1, 2, or 4) */ in ich_num_aprs()
58 int aprmax = 1 << (cs->vprebits - 5); in ich_num_aprs()
59 assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); in ich_num_aprs()
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
88 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
155 u32 l3cc_table[GEN9_MOCS_SIZE / 2];
168 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
169 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
170 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
171 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
180 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
192 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { in load_render_mocs()
[all …]
/openbmc/u-boot/drivers/spi/
H A Domap3_spi.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
43 /* per-register bitmasks */
44 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
45 #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
52 #define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
57 #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
73 #define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
104 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
105 /* channel1: 0x40 - 0x50, bus 0 & 1 */
[all …]
/openbmc/u-boot/drivers/video/
H A Dhitachi_tx18d42vm_lcd.c1 // SPDX-License-Identifier: GPL-2.0+
18 static void lcd_panel_spi_write(int cs, int clk, int mosi, in lcd_panel_spi_write() argument
23 gpio_direction_output(cs, 0); in lcd_panel_spi_write()
26 offset = (bits - 1) - i; in lcd_panel_spi_write()
28 udelay(2); in lcd_panel_spi_write()
30 udelay(2); in lcd_panel_spi_write()
32 gpio_direction_output(cs, 1); in lcd_panel_spi_write()
33 udelay(2); in lcd_panel_spi_write()
44 0x3ca4, /* enter test mode(2) */ in hitachi_tx18d42vm_init()
46 0x4041, /* adopt 2 line / 1 dot */ in hitachi_tx18d42vm_init()
[all …]
/openbmc/linux/include/linux/mfd/syscon/
H A Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
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