Lines Matching +full:cs +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
43 /* per-register bitmasks */
44 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
45 #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
52 #define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
57 #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
73 #define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
104 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
105 /* channel1: 0x40 - 0x50, bus 0 & 1 */
106 /* channel2: 0x54 - 0x64, bus 0 & 1 */
107 /* channel3: 0x68 - 0x78, bus 0 */
115 unsigned int cs; member
124 writel(val, &priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
126 readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
131 writel(enable, &priv->regs->channel[priv->cs].chctrl); in omap3_spi_set_enable()
133 readl(&priv->regs->channel[priv->cs].chctrl); in omap3_spi_set_enable()
142 chconf = readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write()
148 chconf |= (priv->wordlen - 1) << 7; in omap3_spi_write()
156 while (!(readl(&priv->regs->channel[priv->cs].chstat) & in omap3_spi_write()
160 readl(&priv->regs->channel[priv->cs].chstat)); in omap3_spi_write()
161 return -1; in omap3_spi_write()
165 unsigned int *tx = &priv->regs->channel[priv->cs].tx; in omap3_spi_write()
166 if (priv->wordlen > 16) in omap3_spi_write()
168 else if (priv->wordlen > 8) in omap3_spi_write()
175 while ((readl(&priv->regs->channel[priv->cs].chstat) & in omap3_spi_write()
197 chconf = readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_read()
203 chconf |= (priv->wordlen - 1) << 7; in omap3_spi_read()
208 writel(0, &priv->regs->channel[priv->cs].tx); in omap3_spi_read()
213 while (!(readl(&priv->regs->channel[priv->cs].chstat) & in omap3_spi_read()
217 readl(&priv->regs->channel[priv->cs].chstat)); in omap3_spi_read()
218 return -1; in omap3_spi_read()
223 if (i == (len - 1)) in omap3_spi_read()
227 unsigned int *rx = &priv->regs->channel[priv->cs].rx; in omap3_spi_read()
228 if (priv->wordlen > 16) in omap3_spi_read()
230 else if (priv->wordlen > 8) in omap3_spi_read()
251 chconf = readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_txrx()
256 /*set TRANSMIT-RECEIVE Mode*/ in omap3_spi_txrx()
258 chconf |= (priv->wordlen - 1) << 7; in omap3_spi_txrx()
266 while (!(readl(&priv->regs->channel[priv->cs].chstat) & in omap3_spi_txrx()
270 readl(&priv->regs->channel[priv->cs].chstat)); in omap3_spi_txrx()
271 return -1; in omap3_spi_txrx()
275 unsigned int *tx = &priv->regs->channel[priv->cs].tx; in omap3_spi_txrx()
276 if (priv->wordlen > 16) in omap3_spi_txrx()
278 else if (priv->wordlen > 8) in omap3_spi_txrx()
285 while (!(readl(&priv->regs->channel[priv->cs].chstat) & in omap3_spi_txrx()
289 readl(&priv->regs->channel[priv->cs].chstat)); in omap3_spi_txrx()
290 return -1; in omap3_spi_txrx()
294 unsigned int *rx = &priv->regs->channel[priv->cs].rx; in omap3_spi_txrx()
295 if (priv->wordlen > 16) in omap3_spi_txrx()
297 else if (priv->wordlen > 8) in omap3_spi_txrx()
318 int ret = -1; in _spi_xfer()
320 if (priv->wordlen < 4 || priv->wordlen > 32) { in _spi_xfer()
321 printf("omap3_spi: invalid wordlen %d\n", priv->wordlen); in _spi_xfer()
322 return -1; in _spi_xfer()
325 if (bitlen % priv->wordlen) in _spi_xfer()
326 return -1; in _spi_xfer()
328 len = bitlen / priv->wordlen; in _spi_xfer()
330 if (bitlen == 0) { /* only change CS */ in _spi_xfer()
331 int chconf = readl(&priv->regs->channel[priv->cs].chconf); in _spi_xfer()
359 confr = readl(&priv->regs->channel[priv->cs].chconf); in _omap3_spi_set_speed()
361 /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */ in _omap3_spi_set_speed()
362 if (priv->freq) { in _omap3_spi_set_speed()
364 > priv->freq) in _omap3_spi_set_speed()
372 confr |= div << 2; in _omap3_spi_set_speed()
381 confr = readl(&priv->regs->channel[priv->cs].chconf); in _omap3_spi_set_mode()
383 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS in _omap3_spi_set_mode()
386 if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { in _omap3_spi_set_mode()
396 if (priv->mode & SPI_CPHA) in _omap3_spi_set_mode()
398 if (priv->mode & SPI_CPOL) in _omap3_spi_set_mode()
402 if (!(priv->mode & SPI_CS_HIGH)) in _omap3_spi_set_mode()
403 confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */ in _omap3_spi_set_mode()
418 confr = readl(&priv->regs->channel[priv->cs].chconf); in _omap3_spi_set_wordlen()
422 confr |= (priv->wordlen - 1) << 7; in _omap3_spi_set_wordlen()
431 writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, ®s->sysconfig); in spi_reset()
433 tmp = readl(®s->sysstatus); in spi_reset()
438 OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, ®s->sysconfig); in spi_reset()
440 writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable); in spi_reset()
448 * to single-channel master mode in _omap3_spi_claim_bus()
450 conf = readl(&priv->regs->modulctrl); in _omap3_spi_claim_bus()
454 writel(conf, &priv->regs->modulctrl); in _omap3_spi_claim_bus()
475 spi_reset(priv->regs); in spi_claim_bus()
489 writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl); in spi_release_bus()
492 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, in spi_setup_slave() argument
500 * with different number of chip selects (CS, channels): in spi_setup_slave()
501 * McSPI1 has 4 CS (bus 0, cs 0 - 3) in spi_setup_slave()
502 * McSPI2 has 2 CS (bus 1, cs 0 - 1) in spi_setup_slave()
503 * McSPI3 has 2 CS (bus 2, cs 0 - 1) in spi_setup_slave()
504 * McSPI4 has 1 CS (bus 3, cs 0) in spi_setup_slave()
517 case 2: in spi_setup_slave()
527 printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus); in spi_setup_slave()
531 if (((bus == 0) && (cs > 3)) || in spi_setup_slave()
532 ((bus == 1) && (cs > 1)) || in spi_setup_slave()
533 ((bus == 2) && (cs > 1)) || in spi_setup_slave()
534 ((bus == 3) && (cs > 0))) { in spi_setup_slave()
535 printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus); in spi_setup_slave()
550 priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs); in spi_setup_slave()
556 priv->regs = regs; in spi_setup_slave()
557 priv->cs = cs; in spi_setup_slave()
558 priv->freq = max_hz; in spi_setup_slave()
559 priv->mode = mode; in spi_setup_slave()
560 priv->wordlen = priv->slave.wordlen; in spi_setup_slave()
563 priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; in spi_setup_slave()
566 return &priv->slave; in spi_setup_slave()
581 struct udevice *bus = dev->parent; in omap3_spi_claim_bus()
585 priv->cs = slave_plat->cs; in omap3_spi_claim_bus()
586 priv->freq = slave_plat->max_hz; in omap3_spi_claim_bus()
595 struct udevice *bus = dev->parent; in omap3_spi_release_bus()
598 writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl); in omap3_spi_release_bus()
605 struct udevice *bus = dev->parent; in omap3_spi_set_wordlen()
609 priv->cs = slave_plat->cs; in omap3_spi_set_wordlen()
610 priv->wordlen = wordlen; in omap3_spi_set_wordlen()
619 const void *blob = gd->fdt_blob; in omap3_spi_probe()
625 priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset); in omap3_spi_probe()
626 if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in")) in omap3_spi_probe()
627 priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; in omap3_spi_probe()
629 priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT; in omap3_spi_probe()
630 priv->wordlen = SPI_DEFAULT_WORDLEN; in omap3_spi_probe()
632 spi_reset(priv->regs); in omap3_spi_probe()
640 struct udevice *bus = dev->parent; in omap3_spi_xfer()
651 priv->freq = speed; in omap3_spi_set_speed()
661 priv->mode = mode; in omap3_spi_set_mode()
690 { .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
691 { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },