Lines Matching +full:cs +full:- +full:2
22 #include "qemu/qemu-print.h"
24 #include "exec/exec-all.h"
25 #include "fpu/softfloat-helpers.h"
28 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) in openrisc_cpu_set_pc() argument
30 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_set_pc()
32 cpu->env.pc = value; in openrisc_cpu_set_pc()
33 cpu->env.dflag = 0; in openrisc_cpu_set_pc()
36 static vaddr openrisc_cpu_get_pc(CPUState *cs) in openrisc_cpu_get_pc() argument
38 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_get_pc()
40 return cpu->env.pc; in openrisc_cpu_get_pc()
43 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, in openrisc_cpu_synchronize_from_tb() argument
46 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_synchronize_from_tb()
48 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); in openrisc_cpu_synchronize_from_tb()
49 cpu->env.pc = tb->pc; in openrisc_cpu_synchronize_from_tb()
52 static void openrisc_restore_state_to_opc(CPUState *cs, in openrisc_restore_state_to_opc() argument
56 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_restore_state_to_opc()
58 cpu->env.pc = data[0]; in openrisc_restore_state_to_opc()
59 cpu->env.dflag = data[1] & 1; in openrisc_restore_state_to_opc()
60 if (data[1] & 2) { in openrisc_restore_state_to_opc()
61 cpu->env.ppc = cpu->env.pc - 4; in openrisc_restore_state_to_opc()
65 static bool openrisc_cpu_has_work(CPUState *cs) in openrisc_cpu_has_work() argument
67 return cs->interrupt_request & (CPU_INTERRUPT_HARD | in openrisc_cpu_has_work()
71 static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) in openrisc_cpu_mmu_index() argument
73 CPUOpenRISCState *env = cpu_env(cs); in openrisc_cpu_mmu_index()
75 if (env->sr & (ifetch ? SR_IME : SR_DME)) { in openrisc_cpu_mmu_index()
77 return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; in openrisc_cpu_mmu_index()
85 info->print_insn = print_insn_or1k; in openrisc_disas_set_info()
90 CPUState *cs = CPU(obj); in openrisc_cpu_reset_hold() local
91 OpenRISCCPU *cpu = OPENRISC_CPU(cs); in openrisc_cpu_reset_hold()
94 if (occ->parent_phases.hold) { in openrisc_cpu_reset_hold()
95 occ->parent_phases.hold(obj, type); in openrisc_cpu_reset_hold()
98 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); in openrisc_cpu_reset_hold()
100 cpu->env.pc = 0x100; in openrisc_cpu_reset_hold()
101 cpu->env.sr = SR_FO | SR_SM; in openrisc_cpu_reset_hold()
102 cpu->env.lock_addr = -1; in openrisc_cpu_reset_hold()
103 cs->exception_index = -1; in openrisc_cpu_reset_hold()
104 cpu_set_fpcsr(&cpu->env, 0); in openrisc_cpu_reset_hold()
107 &cpu->env.fp_status); in openrisc_cpu_reset_hold()
112 set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); in openrisc_cpu_reset_hold()
116 cpu->env.picmr = 0x00000000; in openrisc_cpu_reset_hold()
117 cpu->env.picsr = 0x00000000; in openrisc_cpu_reset_hold()
119 cpu->env.ttmr = 0x00000000; in openrisc_cpu_reset_hold()
127 CPUState *cs = CPU(cpu); in openrisc_cpu_set_irq() local
137 cpu->env.picsr |= irq_bit; in openrisc_cpu_set_irq()
139 cpu->env.picsr &= ~irq_bit; in openrisc_cpu_set_irq()
142 if (cpu->env.picsr & cpu->env.picmr) { in openrisc_cpu_set_irq()
143 cpu_interrupt(cs, CPU_INTERRUPT_HARD); in openrisc_cpu_set_irq()
145 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); in openrisc_cpu_set_irq()
152 CPUState *cs = CPU(dev); in openrisc_cpu_realizefn() local
156 cpu_exec_realizefn(cs, &local_err); in openrisc_cpu_realizefn()
162 qemu_init_vcpu(cs); in openrisc_cpu_realizefn()
163 cpu_reset(cs); in openrisc_cpu_realizefn()
165 occ->parent_realize(dev, errp); in openrisc_cpu_realizefn()
193 cpu->env.vr = 0x13000008; in or1200_initfn()
194 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; in or1200_initfn()
195 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | in or1200_initfn()
199 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) in or1200_initfn()
200 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in or1200_initfn()
201 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) in or1200_initfn()
202 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in or1200_initfn()
209 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ in openrisc_any_initfn()
210 cpu->env.vr2 = 0; /* No version specific id */ in openrisc_any_initfn()
211 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ in openrisc_any_initfn()
213 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; in openrisc_any_initfn()
214 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | in openrisc_any_initfn()
218 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) in openrisc_any_initfn()
219 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in openrisc_any_initfn()
220 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) in openrisc_any_initfn()
221 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in openrisc_any_initfn()
225 #include "hw/core/sysemu-cpu-ops.h"
232 #include "hw/core/tcg-cpu-ops.h"
255 &occ->parent_realize); in openrisc_cpu_class_init()
257 &occ->parent_phases); in openrisc_cpu_class_init()
259 cc->class_by_name = openrisc_cpu_class_by_name; in openrisc_cpu_class_init()
260 cc->has_work = openrisc_cpu_has_work; in openrisc_cpu_class_init()
261 cc->mmu_index = openrisc_cpu_mmu_index; in openrisc_cpu_class_init()
262 cc->dump_state = openrisc_cpu_dump_state; in openrisc_cpu_class_init()
263 cc->set_pc = openrisc_cpu_set_pc; in openrisc_cpu_class_init()
264 cc->get_pc = openrisc_cpu_get_pc; in openrisc_cpu_class_init()
265 cc->gdb_read_register = openrisc_cpu_gdb_read_register; in openrisc_cpu_class_init()
266 cc->gdb_write_register = openrisc_cpu_gdb_write_register; in openrisc_cpu_class_init()
268 dc->vmsd = &vmstate_openrisc_cpu; in openrisc_cpu_class_init()
269 cc->sysemu_ops = &openrisc_sysemu_ops; in openrisc_cpu_class_init()
271 cc->gdb_num_core_regs = 32 + 3; in openrisc_cpu_class_init()
272 cc->disas_set_info = openrisc_disas_set_info; in openrisc_cpu_class_init()
273 cc->tcg_ops = &openrisc_tcg_ops; in openrisc_cpu_class_init()