Lines Matching +full:cs +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0
28 #define SPD_DEV_TYPE_BYTE 2
33 #define SPD_MODULE_TYPE_UDIMM 2
169 u32 min_write_recovery_time; /* DDR3/2 only */
170 u32 min_write_to_read_cmd_delay; /* DDR3/2 only */
171 u32 min_read_to_prech_cmd_delay; /* DDR3/2 only */
173 u32 min_refresh_recovery; /* DDR3/2 only */
196 * Name: ddr3_get_dimm_num - Find number of dimms and their addresses
198 * Args: dimm_addr - array of dimm addresses
211 dimm_cur_addr--) { in ddr3_get_dimm_num()
214 /* Far-End DIMM must be connected */ in ddr3_get_dimm_num()
232 * Name: dimmSpdInit - Get the SPD parameters.
234 * Args: dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator.
235 * info - DIMM information structure.
261 info->err_check_type = 0; in ddr3_spd_init()
265 info->err_check_type = 1; in ddr3_spd_init()
267 DEBUG_INIT_FULL_C("DRAM err_check_type ", info->err_check_type, 1); in ddr3_spd_init()
271 info->type_info = SPD_MODULE_TYPE_RDIMM; in ddr3_spd_init()
273 case 2: in ddr3_spd_init()
275 info->type_info = SPD_MODULE_TYPE_UDIMM; in ddr3_spd_init()
279 info->type_info = (spd_data[SPD_MODULE_TYPE_BYTE]); in ddr3_spd_init()
285 /* Number Of Row Addresses - 12/13/14/15/16 */ in ddr3_spd_init()
286 info->num_of_row_addr = in ddr3_spd_init()
289 info->num_of_row_addr += SPD_ROW_NUM_MIN; in ddr3_spd_init()
290 DEBUG_INIT_FULL_C("DRAM num_of_row_addr ", info->num_of_row_addr, 2); in ddr3_spd_init()
292 /* Number Of Column Addresses - 9/10/11/12 */ in ddr3_spd_init()
293 info->num_of_col_addr = in ddr3_spd_init()
296 info->num_of_col_addr += SPD_COL_NUM_MIN; in ddr3_spd_init()
297 DEBUG_INIT_FULL_C("DRAM num_of_col_addr ", info->num_of_col_addr, 1); in ddr3_spd_init()
299 /* Number Of Ranks = number of CS on Dimm - 1/2/3/4 Ranks */ in ddr3_spd_init()
300 info->num_of_module_ranks = in ddr3_spd_init()
303 info->num_of_module_ranks += SPD_MODULE_BANK_NUM_MIN; in ddr3_spd_init()
304 DEBUG_INIT_FULL_C("DRAM numOfModuleBanks ", info->num_of_module_ranks, in ddr3_spd_init()
307 /* Data Width - 8/16/32/64 bits */ in ddr3_spd_init()
308 info->data_width = in ddr3_spd_init()
310 DEBUG_INIT_FULL_C("DRAM data_width ", info->data_width, 1); in ddr3_spd_init()
312 /* Number Of Banks On Each Device - 8/16/32/64 banks */ in ddr3_spd_init()
313 info->num_of_banks_on_each_device = in ddr3_spd_init()
316 info->num_of_banks_on_each_device, 1); in ddr3_spd_init()
318 /* Total SDRAM capacity - 256Mb/512Mb/1Gb/2Gb/4Gb/8Gb/16Gb - MegaBits */ in ddr3_spd_init()
319 info->sdram_capacity = in ddr3_spd_init()
322 /* Sdram Width - 4/8/16/32 bits */ in ddr3_spd_init()
323 info->sdram_width = 1 << (2 + (spd_data[SPD_MODULE_ORG_BYTE] & in ddr3_spd_init()
325 DEBUG_INIT_FULL_C("DRAM sdram_width ", info->sdram_width, 1); in ddr3_spd_init()
327 /* CS (Rank) Capacity - MB */ in ddr3_spd_init()
332 /* Jedec SPD DDR3 - page 7, Save spd_data in Mb - 2048=2GB */ in ddr3_spd_init()
334 info->rank_capacity = in ddr3_spd_init()
335 ((1 << info->sdram_capacity) * 256 * in ddr3_spd_init()
336 (info->data_width / info->sdram_width)) << 16; in ddr3_spd_init()
337 /* CS size = CS size / 2 */ in ddr3_spd_init()
339 info->rank_capacity = in ddr3_spd_init()
340 ((1 << info->sdram_capacity) * 256 * in ddr3_spd_init()
341 (info->data_width / info->sdram_width) * 0x2) << 16; in ddr3_spd_init()
342 /* 0x2 => 0x100000-1Mbit / 8-bit->byte / 0x10000 */ in ddr3_spd_init()
344 DEBUG_INIT_FULL_C("DRAM rank_capacity[31] ", info->rank_capacity, 1); in ddr3_spd_init()
347 info->num_of_devices = in ddr3_spd_init()
348 ((info->data_width / info->sdram_width) * in ddr3_spd_init()
349 info->num_of_module_ranks) + info->err_check_type; in ddr3_spd_init()
350 DEBUG_INIT_FULL_C("DRAM num_of_devices ", info->num_of_devices, 1); in ddr3_spd_init()
352 /* Address Mapping from Edge connector to DRAM - mirroring option */ in ddr3_spd_init()
353 info->addr_mirroring = in ddr3_spd_init()
356 /* Timings - All in ps */ in ddr3_spd_init()
362 info->min_cycle_time = spd_data[SPD_TCK_BYTE] * time_base; in ddr3_spd_init()
363 DEBUG_INIT_FULL_C("DRAM tCKmin ", info->min_cycle_time, 1); in ddr3_spd_init()
371 info->refresh_interval = 7800000; /* Set to 7.8uSec */ in ddr3_spd_init()
372 DEBUG_INIT_FULL_C("DRAM refresh_interval ", info->refresh_interval, 1); in ddr3_spd_init()
374 /* Suported Cas Latencies - DDR 3: */ in ddr3_spd_init()
378 *******-******-******-******-******-******-******-*******-******* in ddr3_spd_init()
380 *********************************************************-******* in ddr3_spd_init()
381 *******-******-******-******-******-******-******-*******-******* in ddr3_spd_init()
383 *******-******-******-******-******-******-******-*******-******* in ddr3_spd_init()
387 /* DDR3 include 2 byte of CAS support */ in ddr3_spd_init()
388 info->supported_cas_latencies = in ddr3_spd_init()
392 info->supported_cas_latencies, 1); in ddr3_spd_init()
395 info->min_cas_lat_time = (spd_data[SPD_TAA_BYTE] * time_base); in ddr3_spd_init()
405 info->min_write_recovery_time = spd_data[SPD_TWR_BYTE] * time_base; in ddr3_spd_init()
407 info->min_write_recovery_time, 1); in ddr3_spd_init()
410 info->min_ras_to_cas_delay = spd_data[SPD_TRCD_BYTE] * time_base; in ddr3_spd_init()
412 info->min_ras_to_cas_delay, 1); in ddr3_spd_init()
415 info->min_row_active_to_row_active = in ddr3_spd_init()
418 info->min_row_active_to_row_active, 1); in ddr3_spd_init()
421 info->min_row_precharge_time = spd_data[SPD_TRP_BYTE] * time_base; in ddr3_spd_init()
423 info->min_row_precharge_time, 1); in ddr3_spd_init()
425 /* Minimum Active to Precharge Delay Time - tRAS ps */ in ddr3_spd_init()
426 info->min_active_to_precharge = in ddr3_spd_init()
428 info->min_active_to_precharge |= spd_data[SPD_TRAS_LSB_BYTE]; in ddr3_spd_init()
429 info->min_active_to_precharge *= time_base; in ddr3_spd_init()
431 info->min_active_to_precharge, 1); in ddr3_spd_init()
433 /* Minimum Refresh Recovery Delay Time - tRFC ps */ in ddr3_spd_init()
434 info->min_refresh_recovery = spd_data[SPD_TRFC_MSB_BYTE] << 8; in ddr3_spd_init()
435 info->min_refresh_recovery |= spd_data[SPD_TRFC_LSB_BYTE]; in ddr3_spd_init()
436 info->min_refresh_recovery *= time_base; in ddr3_spd_init()
438 info->min_refresh_recovery, 1); in ddr3_spd_init()
444 info->min_write_to_read_cmd_delay = spd_data[SPD_TWTR_BYTE] * time_base; in ddr3_spd_init()
446 info->min_write_to_read_cmd_delay, 1); in ddr3_spd_init()
452 info->min_read_to_prech_cmd_delay = spd_data[SPD_TRTP_BYTE] * time_base; in ddr3_spd_init()
454 info->min_read_to_prech_cmd_delay, 1); in ddr3_spd_init()
462 info->min_four_active_win_delay = tmp * time_base; in ddr3_spd_init()
464 info->min_four_active_win_delay, 1); in ddr3_spd_init()
468 if (info->type_info == SPD_MODULE_TYPE_RDIMM) { in ddr3_spd_init()
469 for (rc = 2; rc < 6; rc += 2) { in ddr3_spd_init()
470 tmp = spd_data[SPD_RDIMM_RC_BYTE + rc / 2]; in ddr3_spd_init()
471 info->dimm_rc[rc] = in ddr3_spd_init()
472 spd_data[SPD_RDIMM_RC_BYTE + rc / 2] & in ddr3_spd_init()
474 info->dimm_rc[rc + 1] = in ddr3_spd_init()
475 (spd_data[SPD_RDIMM_RC_BYTE + rc / 2] >> 4) & in ddr3_spd_init()
481 info->vendor = (vendor_high << 8) + vendor_low; in ddr3_spd_init()
482 DEBUG_INIT_C("DDR3 Training Sequence - Registered DIMM vendor ID 0x", in ddr3_spd_init()
483 info->vendor, 4); in ddr3_spd_init()
485 info->dimm_rc[0] = RDIMM_RC0; in ddr3_spd_init()
486 info->dimm_rc[1] = RDIMM_RC1; in ddr3_spd_init()
487 info->dimm_rc[2] = RDIMM_RC2; in ddr3_spd_init()
488 info->dimm_rc[8] = RDIMM_RC8; in ddr3_spd_init()
489 info->dimm_rc[9] = RDIMM_RC9; in ddr3_spd_init()
490 info->dimm_rc[10] = RDIMM_RC10; in ddr3_spd_init()
491 info->dimm_rc[11] = RDIMM_RC11; in ddr3_spd_init()
499 * Name: ddr3_spd_sum_init - Get the SPD parameters.
501 * Args: dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator.
502 * info - DIMM information structure.
512 if (sum_info->type_info != info->type_info) { in ddr3_spd_sum_init()
513 DEBUG_INIT_S("DDR3 Dimm Compare - DIMM type does not match - FAIL\n"); in ddr3_spd_sum_init()
516 if (sum_info->err_check_type > info->err_check_type) { in ddr3_spd_sum_init()
517 sum_info->err_check_type = info->err_check_type; in ddr3_spd_sum_init()
518 DEBUG_INIT_S("DDR3 Dimm Compare - ECC does not match. ECC is disabled\n"); in ddr3_spd_sum_init()
520 if (sum_info->data_width != info->data_width) { in ddr3_spd_sum_init()
521 DEBUG_INIT_S("DDR3 Dimm Compare - DRAM bus width does not match - FAIL\n"); in ddr3_spd_sum_init()
524 if (sum_info->min_cycle_time < info->min_cycle_time) in ddr3_spd_sum_init()
525 sum_info->min_cycle_time = info->min_cycle_time; in ddr3_spd_sum_init()
526 if (sum_info->refresh_interval < info->refresh_interval) in ddr3_spd_sum_init()
527 sum_info->refresh_interval = info->refresh_interval; in ddr3_spd_sum_init()
528 sum_info->supported_cas_latencies &= info->supported_cas_latencies; in ddr3_spd_sum_init()
529 if (sum_info->min_cas_lat_time < info->min_cas_lat_time) in ddr3_spd_sum_init()
530 sum_info->min_cas_lat_time = info->min_cas_lat_time; in ddr3_spd_sum_init()
531 if (sum_info->min_write_recovery_time < info->min_write_recovery_time) in ddr3_spd_sum_init()
532 sum_info->min_write_recovery_time = in ddr3_spd_sum_init()
533 info->min_write_recovery_time; in ddr3_spd_sum_init()
534 if (sum_info->min_ras_to_cas_delay < info->min_ras_to_cas_delay) in ddr3_spd_sum_init()
535 sum_info->min_ras_to_cas_delay = info->min_ras_to_cas_delay; in ddr3_spd_sum_init()
536 if (sum_info->min_row_active_to_row_active < in ddr3_spd_sum_init()
537 info->min_row_active_to_row_active) in ddr3_spd_sum_init()
538 sum_info->min_row_active_to_row_active = in ddr3_spd_sum_init()
539 info->min_row_active_to_row_active; in ddr3_spd_sum_init()
540 if (sum_info->min_row_precharge_time < info->min_row_precharge_time) in ddr3_spd_sum_init()
541 sum_info->min_row_precharge_time = info->min_row_precharge_time; in ddr3_spd_sum_init()
542 if (sum_info->min_active_to_precharge < info->min_active_to_precharge) in ddr3_spd_sum_init()
543 sum_info->min_active_to_precharge = in ddr3_spd_sum_init()
544 info->min_active_to_precharge; in ddr3_spd_sum_init()
545 if (sum_info->min_refresh_recovery < info->min_refresh_recovery) in ddr3_spd_sum_init()
546 sum_info->min_refresh_recovery = info->min_refresh_recovery; in ddr3_spd_sum_init()
547 if (sum_info->min_write_to_read_cmd_delay < in ddr3_spd_sum_init()
548 info->min_write_to_read_cmd_delay) in ddr3_spd_sum_init()
549 sum_info->min_write_to_read_cmd_delay = in ddr3_spd_sum_init()
550 info->min_write_to_read_cmd_delay; in ddr3_spd_sum_init()
551 if (sum_info->min_read_to_prech_cmd_delay < in ddr3_spd_sum_init()
552 info->min_read_to_prech_cmd_delay) in ddr3_spd_sum_init()
553 sum_info->min_read_to_prech_cmd_delay = in ddr3_spd_sum_init()
554 info->min_read_to_prech_cmd_delay; in ddr3_spd_sum_init()
555 if (sum_info->min_four_active_win_delay < in ddr3_spd_sum_init()
556 info->min_four_active_win_delay) in ddr3_spd_sum_init()
557 sum_info->min_four_active_win_delay = in ddr3_spd_sum_init()
558 info->min_four_active_win_delay; in ddr3_spd_sum_init()
559 if (sum_info->min_write_to_read_cmd_delay < in ddr3_spd_sum_init()
560 info->min_write_to_read_cmd_delay) in ddr3_spd_sum_init()
561 sum_info->min_write_to_read_cmd_delay = in ddr3_spd_sum_init()
562 info->min_write_to_read_cmd_delay; in ddr3_spd_sum_init()
570 * Args: ecc_ena - User ECC setup
578 MV_DIMM_INFO dimm_info[2];
581 u32 cs, cl, cs_num, cs_ena; local
586 __maybe_unused u32 dimm_addr[2] = { 0, 0 };
589 /* Armada 370 - SPD is not available on DIMM */
591 * Set MC registers according to Static SPD values Values -
610 /* Dynamic D-Unit Setup - Read SPD values */
615 DEBUG_INIT_S("DDR3 Training Sequence - No DIMMs detected\n");
617 DEBUG_INIT_S("DDR3 Training Sequence - FAILED (Wrong DIMMs Setup)\n");
621 DEBUG_INIT_C("DDR3 Training Sequence - Number of DIMMs detected: ",
637 /* Set number of enabled CS */
647 DEBUG_INIT_C("DDR3 Training Sequence - Number of CS exceed limit - ",
652 /* Set bitmap of enabled CS */
661 for (cs = 0; cs < MAX_CS; cs += 2) {
662 if (((1 << cs) & DIMM_CS_BITMAP) &&
663 !(cs_ena & (1 << cs))) {
665 cs_ena |= (0x1 << cs);
666 else if (dimm_info[dimm].num_of_module_ranks == 2)
667 cs_ena |= (0x3 << cs);
669 cs_ena |= (0x7 << cs);
671 cs_ena |= (0xF << cs);
682 DEBUG_INIT_C("DDR3 Training Sequence - Number of enabled CS exceed limit - ",
687 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Number of CS = ", cs_num, 1);
689 /* Check Ratio - '1' - 2:1, '0' - 1:1 */
691 ddr_clk_time = hclk_time / 2;
697 reg = (reg_read(REG_DDR3_MR0_ADDR) >> 2);
709 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Cas Latency = ", cl, 1);
711 /* {0x00001400} - DDR SDRAM Configuration Register */
719 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Enabled\n");
721 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Disabled\n");
726 DEBUG_INIT_S("DDR3 Training Sequence - FAIL - Illegal R-DIMM setup\n");
730 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - R-DIMM\n");
732 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - U-DIMM\n");
742 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 64Bits\n");
744 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");
747 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");
753 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");
755 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");
767 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - RefreshInterval/Hclk = ", tmp, 4);
771 reg |= (1 << 16); /* If 2:1 need to set P2DWr */
778 /*{0x00001404} - DDR SDRAM Configuration Register */
785 /* {0x00001408} - DDR SDRAM Timing (Low) Register */
788 /* tRAS - (0:3,20) */
794 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRAS-1 = ", tmp, 1);
798 /* tRCD - (4:7) */
803 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRCD-1 = ", tmp, 1);
806 /* tRP - (8:11) */
811 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRP-1 = ", tmp, 1);
814 /* tWR - (12:15) */
819 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tWR-1 = ", tmp, 1);
822 /* tWTR - (16:19) */
827 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tWTR-1 = ", tmp, 1);
830 /* tRRD - (24:27) */
835 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRRD-1 = ", tmp, 1);
838 /* tRTP - (28:31) */
843 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRTP-1 = ", tmp, 1);
851 /*{0x0000140C} - DDR SDRAM Timing (High) Register */
855 /* tRFC - (0:6,16:18) */
860 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRFC-1 = ", tmp, 1);
865 /*{0x00001410} - DDR SDRAM Address Control Register */
868 /* tFAW - (24:28) */
875 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tFAW = ", tmp, 1);
878 tmp = sum_info.min_four_active_win_delay -
884 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tFAW-4*tRRD = ", tmp, 1);
896 for (cs = 0; cs < MAX_CS; cs++) {
897 if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
906 (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs)));
910 (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs)));
912 (REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS + cs));
920 for (cs = 0; cs < MAX_CS; cs++) {
921 if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
928 reg |= (1 << (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs));
934 /*{0x00001418} - DDR SDRAM Operation Register */
936 for (cs = 0; cs < MAX_CS; cs++) {
937 if (cs_ena & (1 << cs))
938 reg &= ~(1 << (cs + REG_SDRAM_OPERATION_CS_OFFS));
942 /*{0x00001420} - DDR SDRAM Extended Mode Register */
946 /*{0x00001424} - DDR Controller Control (High) Register */
954 /*{0x0000142C} - DDR3 Timing Register */
961 /*{0x00001484} - MBus CPU Block Register */
968 * In case of mixed dimm and on-board devices setup paramters will
971 /*{0x00001494} - DDR SDRAM ODT Control (Low) Register */
975 /*{0x00001498} - DDR SDRAM ODT Control (High) Register */
979 /*{0x0000149C} - DDR Dunit ODT Control Register */
983 /*{0x000014A0} - DDR Dunit ODT Control Register */
989 /*{0x000014C0} - DRAM address and Control Driving Strenght */
992 /*{0x000014C4} - DRAM Data and DQS Driving Strenght */
996 /*{0x000014CC} - DRAM Main Pads Calibration Machine Control Register */
1003 /* 0x14CC[4:3] - CalUpdateControl = IntOnly */
1013 for (cs = 0; cs < MAX_CS; cs++) {
1014 if ((1 << cs) & DIMM_CS_BITMAP) {
1015 if ((1 << cs) & cs_ena) {
1022 reg_write(REG_CS_SIZE_SCRATCH_ADDR + (cs * 0x8),
1023 dimm_info[dimm_cnt].rank_capacity - 1);
1025 reg_write(REG_CS_SIZE_SCRATCH_ADDR + (cs * 0x8), 0);
1031 /*{0x00020184} - Close FastPath - 2G */
1034 /*{0x00001538} - Read Data Sample Delays Register */
1036 for (cs = 0; cs < MAX_CS; cs++) {
1037 if (cs_ena & (1 << cs))
1038 reg |= (cl << (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs));
1042 DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Read Data Sample Delays = ", reg,
1045 /*{0x0000153C} - Read Data Ready Delay Register */
1047 for (cs = 0; cs < MAX_CS; cs++) {
1048 if (cs_ena & (1 << cs)) {
1049 reg |= ((cl + 2) <<
1050 (REG_READ_DATA_READY_DELAYS_OFFS * cs));
1054 DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Read Data Ready Delays = ", reg, 1);
1060 reg |= ((tmp & 0x1) << 2);
1062 for (cs = 0; cs < MAX_CS; cs++) {
1063 if (cs_ena & (1 << cs)) {
1065 (cs << MR_CS_ADDR_OFFS), reg);
1074 for (cs = 0; cs < MAX_CS; cs++) {
1075 if (cs_ena & (1 << cs)) {
1076 reg |= odt_static[cs_ena][cs];
1078 (cs << MR_CS_ADDR_OFFS), reg);
1084 tmp = hclk_time / 2;
1109 reg = ((cwl - 5) << REG_DDR3_MR2_CWL_OFFS);
1111 for (cs = 0; cs < MAX_CS; cs++) {
1112 if (cs_ena & (1 << cs)) {
1114 reg |= odt_dynamic[cs_ena][cs];
1116 (cs << MR_CS_ADDR_OFFS), reg);
1122 for (cs = 0; cs < MAX_CS; cs++) {
1123 if (cs_ena & (1 << cs)) {
1125 (cs << MR_CS_ADDR_OFFS), reg);
1129 /* {0x00001428} - DDR ODT Timing (Low) Register */
1131 reg |= (((cl - cwl + 1) & 0xF) << 4);
1132 reg |= (((cl - cwl + 6) & 0xF) << 8);
1133 reg |= ((((cl - cwl + 6) >> 4) & 0x1) << 21);
1134 reg |= (((cl - 1) & 0xF) << 12);
1138 /* {0x0000147C} - DDR ODT Timing (High) Register */
1140 reg |= ((cwl - 1) << 8);
1145 /*{0x000015E0} - DDR3 Rank Control Register */
1149 for (cs = 0; cs < MAX_CS; cs++) {
1150 if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
1158 (cs == 1 || cs == 3) &&
1160 reg |= (1 << (REG_DDR3_RANK_CTRL_MIRROR_OFFS + cs));
1161 DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Setting Address Mirroring for CS = ",
1162 cs, 1);
1169 /*{0xD00015E4} - ZQDS Configuration Register */
1173 /* {0x00015EC} - DDR PHY */
1187 /* Registered DIMM support - supported only in AXP A0 devices */
1194 DEBUG_INIT_S("DDR3 Training Sequence - Registered DIMM detected\n");
1202 /* De-assert M_RESETn and assert M_CKE */
1219 /* Configure - Set Delay - tSTAB/tMRD */
1220 if (rc == 2 || rc == 10)
1222 /* 0x1418 - SDRAM Operation Register */
1242 * Name: ddr3_div - this function divides integers
1244 * Args: val - the value
1245 * divider - the divider
1246 * sub - substruction value
1252 return val / divider + (val % divider > 0 ? 1 : 0) - sub;