Lines Matching +full:cs +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0
46 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
59 * Args: freq - current sequence frequency
60 * dram_info - main struct
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
70 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
103 * Read results to arrays - Results are required for WL in ddr3_write_leveling_hw()
106 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
107 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
109 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
111 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw()
112 && dram_info->ecc_ena) in ddr3_write_leveling_hw()
115 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw()
121 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
124 WL_HI_FREQ_STATE - 1; in ddr3_write_leveling_hw()
127 cs, pup); in ddr3_write_leveling_hw()
128 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw()
133 /* Debug message - Print res for cs[i]: cs,PUP,Phase,Delay */ in ddr3_write_leveling_hw()
134 DEBUG_WL_S("DDR3 - Write Leveling - Write Leveling Cs - "); in ddr3_write_leveling_hw()
135 DEBUG_WL_D((u32) cs, 1); in ddr3_write_leveling_hw()
138 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
140 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw()
141 && dram_info->ecc_ena) in ddr3_write_leveling_hw()
143 DEBUG_WL_S("DDR3 - Write Leveling - PUP: "); in ddr3_write_leveling_hw()
147 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw()
151 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw()
152 [D], 2); in ddr3_write_leveling_hw()
168 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n"); in ddr3_write_leveling_hw()
172 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Error\n"); in ddr3_write_leveling_hw()
180 * Args: dram_info - main struct
186 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
193 ddr_width = dram_info->ddr_width; in ddr3_wl_supplement()
196 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - Starting\n"); in ddr3_wl_supplement()
199 /* Data error from pos-adge to pos-adge */ in ddr3_wl_supplement()
213 DEBUG_WL_S("Error - bus width!!!\n"); in ddr3_wl_supplement()
221 /* [0] = 1 - Enable SW override */ in ddr3_wl_supplement()
222 /* 0x15B8 - Training SW 2 Register */ in ddr3_wl_supplement()
224 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - SW Override Enabled\n"); in ddr3_wl_supplement()
226 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_wl_supplement()
228 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
229 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
232 * 2 iterations loop: 1)actual WL results 2) fix WL in ddr3_wl_supplement()
237 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); in ddr3_wl_supplement()
246 dram_info->num_of_std_pups * (1 - in ddr3_wl_supplement()
249 /* ECC Support - Switch ECC Mux on ecc=1 */ in ddr3_wl_supplement()
255 (dram_info->ecc_ena * in ddr3_wl_supplement()
293 /* ECC support - bit 8 */ in ddr3_wl_supplement()
300 tmp_pup = pup - 4; in ddr3_wl_supplement()
306 DEBUG_WL_D((u32) cs, 1); in ddr3_wl_supplement()
314 sdram_pup_val, 2); in ddr3_wl_supplement()
317 + pup), 2); in ddr3_wl_supplement()
324 pup) - sdram_pup_val; in ddr3_wl_supplement()
330 sdram_pup_val - in ddr3_wl_supplement()
333 DEBUG_WL_C("err = ", err, 2); in ddr3_wl_supplement()
335 2); in ddr3_wl_supplement()
337 /* PUP is correct - increment State */ in ddr3_wl_supplement()
338 dram_info->wl_val[cs] in ddr3_wl_supplement()
344 ((dram_info->wl_val in ddr3_wl_supplement()
345 [cs] in ddr3_wl_supplement()
349 dram_info->wl_val[cs] in ddr3_wl_supplement()
353 dram_info->wl_val in ddr3_wl_supplement()
354 [cs][pup_num] in ddr3_wl_supplement()
358 (PUP_WL_MODE, cs, in ddr3_wl_supplement()
359 pup * (1 - ecc) + in ddr3_wl_supplement()
365 dram_info->wl_val in ddr3_wl_supplement()
366 [cs][pup_num] in ddr3_wl_supplement()
369 dram_info->wl_val in ddr3_wl_supplement()
370 [cs][pup_num] in ddr3_wl_supplement()
377 DEBUG_WL_S("#### Warning - Possible Layout Violation (DQS is longer than CLK)####\n"); in ddr3_wl_supplement()
382 dram_info->wl_val[cs] in ddr3_wl_supplement()
385 dram_info->wl_val[cs] in ddr3_wl_supplement()
389 (PUP_WL_MODE, cs, in ddr3_wl_supplement()
390 pup * (1 - ecc) + in ddr3_wl_supplement()
398 /* ECC Support - Disable ECC MUX */ in ddr3_wl_supplement()
408 for (pup = 0; pup < dram_info->num_of_std_pups; pup++) in ddr3_wl_supplement()
409 sum += dram_info->wl_val[cs][pup][S]; in ddr3_wl_supplement()
411 if (dram_info->ecc_ena) in ddr3_wl_supplement()
412 sum += dram_info->wl_val[cs][ECC_PUP][S]; in ddr3_wl_supplement()
415 if (sum < (WL_HI_FREQ_STATE * (dram_info->num_of_total_pups))) { in ddr3_wl_supplement()
416 DEBUG_WL_C("DDR3 - Write Leveling Hi-Freq Supplement - didn't work for Cs - ", in ddr3_wl_supplement()
417 (u32) cs, 1); in ddr3_wl_supplement()
424 dram_info->wl_max_phase = 0; in ddr3_wl_supplement()
425 dram_info->wl_min_phase = 10; in ddr3_wl_supplement()
428 * Read results to arrays - Results are required for DQS Centralization in ddr3_wl_supplement()
430 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
431 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
432 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_wl_supplement()
433 if (pup == dram_info->num_of_std_pups in ddr3_wl_supplement()
434 && dram_info->ecc_ena) in ddr3_wl_supplement()
436 reg = ddr3_read_pup_reg(PUP_WL_MODE, cs, pup); in ddr3_wl_supplement()
440 if (phase > dram_info->wl_max_phase) in ddr3_wl_supplement()
441 dram_info->wl_max_phase = phase; in ddr3_wl_supplement()
442 if (phase < dram_info->wl_min_phase) in ddr3_wl_supplement()
443 dram_info->wl_min_phase = phase; in ddr3_wl_supplement()
448 /* Disable SW override - Must be in a different stage */ in ddr3_wl_supplement()
449 /* [0]=0 - Enable SW override */ in ddr3_wl_supplement()
452 /* 0x15B8 - Training SW 2 Register */ in ddr3_wl_supplement()
459 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - Ended Successfully\n"); in ddr3_wl_supplement()
467 * Args: freq - current sequence frequency
468 * dram_info - main struct
474 u32 reg, phase, delay, cs, pup, pup_num; in ddr3_write_leveling_hw_reg_dimm() local
477 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw_reg_dimm()
478 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw_reg_dimm()
480 if (dram_info->num_cs > 2) { in ddr3_write_leveling_hw_reg_dimm()
481 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n"); in ddr3_write_leveling_hw_reg_dimm()
488 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_hw_reg_dimm()
509 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw_reg_dimm()
510 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw_reg_dimm()
526 * Read results to arrays - Results are required for WL High in ddr3_write_leveling_hw_reg_dimm()
529 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
530 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
532 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
534 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw_reg_dimm()
535 && dram_info->ecc_ena) in ddr3_write_leveling_hw_reg_dimm()
538 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
544 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw_reg_dimm()
545 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw_reg_dimm()
552 cs, pup, 0, in ddr3_write_leveling_hw_reg_dimm()
554 dram_info->wl_val[cs][pup][P] = in ddr3_write_leveling_hw_reg_dimm()
556 dram_info->wl_val[cs][pup][D] = in ddr3_write_leveling_hw_reg_dimm()
559 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw_reg_dimm()
560 WL_HI_FREQ_STATE - 1; in ddr3_write_leveling_hw_reg_dimm()
563 cs, pup); in ddr3_write_leveling_hw_reg_dimm()
564 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw_reg_dimm()
569 * Debug message - Print res for cs[i]: in ddr3_write_leveling_hw_reg_dimm()
570 * cs,PUP,Phase,Delay in ddr3_write_leveling_hw_reg_dimm()
572 DEBUG_WL_S("DDR3 - Write Leveling - Write Leveling Cs - "); in ddr3_write_leveling_hw_reg_dimm()
573 DEBUG_WL_D((u32) cs, 1); in ddr3_write_leveling_hw_reg_dimm()
576 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
579 ("DDR3 - Write Leveling - PUP: "); in ddr3_write_leveling_hw_reg_dimm()
583 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw_reg_dimm()
587 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw_reg_dimm()
588 [D], 2); in ddr3_write_leveling_hw_reg_dimm()
603 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n"); in ddr3_write_leveling_hw_reg_dimm()
608 for (pup = 0; pup <= dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
618 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
619 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
621 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
623 /* ECC support - bit 8 */ in ddr3_write_leveling_hw_reg_dimm()
624 pup_num = (pup == dram_info->num_of_std_pups) ? in ddr3_write_leveling_hw_reg_dimm()
626 ddr3_write_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
637 for (pup = 0; pup <= dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
644 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n"); in ddr3_write_leveling_hw_reg_dimm()
652 * Args: freq - current sequence frequency
653 * dram_info - main struct
659 u32 reg, cs, cnt, pup, max_pup_num; in ddr3_write_leveling_sw() local
661 max_pup_num = dram_info->num_of_total_pups; in ddr3_write_leveling_sw()
664 /* Debug message - Start Write leveling procedure */ in ddr3_write_leveling_sw()
665 DEBUG_WL_S("DDR3 - Write Leveling - Starting SW WL procedure\n"); in ddr3_write_leveling_sw()
677 /* Set Output buffer-off to all CS and correct ODT values */ in ddr3_write_leveling_sw()
678 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
679 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
682 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
685 /* 0x15D0 - DDR3 MR0 Register */ in ddr3_write_leveling_sw()
687 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw()
689 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
691 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_write_leveling_sw()
692 * enable current cs in ddr3_write_leveling_sw()
694 /* 0x1418 - SDRAM Operation Register */ in ddr3_write_leveling_sw()
701 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Qoff and RTT Values are set for all Cs\n"); in ddr3_write_leveling_sw()
706 /* [0] = 1 - Enable SW override */ in ddr3_write_leveling_sw()
707 /* 0x15B8 - Training SW 2 Register */ in ddr3_write_leveling_sw()
709 DEBUG_WL_FULL_S("DDR3 - Write Leveling - SW Override Enabled\n"); in ddr3_write_leveling_sw()
714 /* [2] = 0 - TrnWLMode - Enable */ in ddr3_write_leveling_sw()
715 /* 0x15B8 - Training SW 2 Register */ in ddr3_write_leveling_sw()
718 memset(dram_info->wl_val, 0, sizeof(u32) * MAX_CS * MAX_PUP_NUM * 7); in ddr3_write_leveling_sw()
720 /* Loop for each cs */ in ddr3_write_leveling_sw()
721 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
722 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
723 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Starting working with Cs - ", in ddr3_write_leveling_sw()
724 (u32) cs, 1); in ddr3_write_leveling_sw()
725 /* Refresh X9 current cs */ in ddr3_write_leveling_sw()
726 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Refresh X9\n"); in ddr3_write_leveling_sw()
731 + cs)); in ddr3_write_leveling_sw()
732 /* [3-0] = 0x2 - refresh, [11-8] - enable current cs */ in ddr3_write_leveling_sw()
733 reg_write(REG_SDRAM_OPERATION_ADDR, reg); /* 0x1418 - SDRAM Operation Register */ in ddr3_write_leveling_sw()
743 /* Configure MR1 in Cs[CsNum] - write leveling on, output buffer on */ in ddr3_write_leveling_sw()
744 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Configure MR1 for current Cs: WL-on,OB-on\n"); in ddr3_write_leveling_sw()
749 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
752 /* [7]=1, [12]=0 - Output Buffer and write leveling enabled */ in ddr3_write_leveling_sw()
753 reg_write(REG_DDR3_MR1_ADDR, reg); /* 0x15D4 - DDR3 MR1 Register */ in ddr3_write_leveling_sw()
754 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw()
756 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
758 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_write_leveling_sw()
759 * enable current cs in ddr3_write_leveling_sw()
761 /* 0x1418 - SDRAM Operation Register */ in ddr3_write_leveling_sw()
766 /* Write leveling cs[cs] */ in ddr3_write_leveling_sw()
768 ddr3_write_leveling_single_cs(cs, freq, ratio_2to1, in ddr3_write_leveling_sw()
769 (u32 *)(res + cs), in ddr3_write_leveling_sw()
771 DEBUG_WL_FULL_C("DDR3 - Write Leveling single Cs - FAILED - Cs - ", in ddr3_write_leveling_sw()
772 (u32) cs, 1); in ddr3_write_leveling_sw()
774 if (((res[cs] >> pup) & 0x1) == 0) { in ddr3_write_leveling_sw()
782 /* Set TrnWLDeUpd - After each CS is done */ in ddr3_write_leveling_sw()
785 /* 0x16AC - Training Write leveling register */ in ddr3_write_leveling_sw()
789 * Debug message - Finished Write leveling cs[cs] - in ddr3_write_leveling_sw()
792 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Finished Cs - ", (u32) cs, in ddr3_write_leveling_sw()
794 DEBUG_WL_FULL_C("DDR3 - Write Leveling - The Results: 1-PUP locked, 0-PUP failed -", in ddr3_write_leveling_sw()
795 (u32) res[cs], 3); in ddr3_write_leveling_sw()
798 * Configure MR1 in cs[cs] - write leveling off (0), in ddr3_write_leveling_sw()
804 /* No need to sort ODT since it is same CS */ in ddr3_write_leveling_sw()
805 /* 0x15D4 - DDR3 MR1 Register */ in ddr3_write_leveling_sw()
807 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw()
809 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
811 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_write_leveling_sw()
812 * enable current cs in ddr3_write_leveling_sw()
814 /* 0x1418 - SDRAM Operation Register */ in ddr3_write_leveling_sw()
822 /* [2]=1 - TrnWLMode - Disable */ in ddr3_write_leveling_sw()
825 /* 0x15B8 - Training SW 2 Register */ in ddr3_write_leveling_sw()
828 /* Disable SW override - Must be in a different stage */ in ddr3_write_leveling_sw()
829 /* [0]=0 - Enable SW override */ in ddr3_write_leveling_sw()
832 /* 0x15B8 - Training SW 2 Register */ in ddr3_write_leveling_sw()
835 /* Set Output buffer-on to all CS and correct ODT values */ in ddr3_write_leveling_sw()
836 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
837 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
841 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
843 /* 0x15D0 - DDR3 MR1 Register */ in ddr3_write_leveling_sw()
845 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw()
847 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
849 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_write_leveling_sw()
850 * enable current cs in ddr3_write_leveling_sw()
852 /* 0x1418 - SDRAM Operation Register */ in ddr3_write_leveling_sw()
867 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Finished WL procedure for all Cs\n"); in ddr3_write_leveling_sw()
876 * Args: freq - current sequence frequency
877 * dram_info - main struct
884 u32 reg, cs, cnt, pup; in ddr3_write_leveling_sw_reg_dimm() local
888 /* Debug message - Start Write leveling procedure */ in ddr3_write_leveling_sw_reg_dimm()
889 DEBUG_WL_S("DDR3 - Write Leveling - Starting SW WL procedure\n"); in ddr3_write_leveling_sw_reg_dimm()
904 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_sw_reg_dimm()
912 /* Set Output buffer-off to all CS and correct ODT values */ in ddr3_write_leveling_sw_reg_dimm()
913 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
914 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
917 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw_reg_dimm()
920 /* 0x15D0 - DDR3 MR0 Register */ in ddr3_write_leveling_sw_reg_dimm()
922 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw_reg_dimm()
924 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
926 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_write_leveling_sw_reg_dimm()
927 * enable current cs in ddr3_write_leveling_sw_reg_dimm()
929 /* 0x1418 - SDRAM Operation Register */ in ddr3_write_leveling_sw_reg_dimm()
936 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Qoff and RTT Values are set for all Cs\n"); in ddr3_write_leveling_sw_reg_dimm()
941 /* [0] = 1 - Enable SW override */ in ddr3_write_leveling_sw_reg_dimm()
942 /* 0x15B8 - Training SW 2 Register */ in ddr3_write_leveling_sw_reg_dimm()
944 DEBUG_WL_FULL_S("DDR3 - Write Leveling - SW Override Enabled\n"); in ddr3_write_leveling_sw_reg_dimm()
949 /* [2] = 0 - TrnWLMode - Enable */ in ddr3_write_leveling_sw_reg_dimm()
950 /* 0x15B8 - Training SW 2 Register */ in ddr3_write_leveling_sw_reg_dimm()
953 /* Loop for each cs */ in ddr3_write_leveling_sw_reg_dimm()
954 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
955 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
956 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Starting working with Cs - ", in ddr3_write_leveling_sw_reg_dimm()
957 (u32) cs, 1); in ddr3_write_leveling_sw_reg_dimm()
959 /* Refresh X9 current cs */ in ddr3_write_leveling_sw_reg_dimm()
960 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Refresh X9\n"); in ddr3_write_leveling_sw_reg_dimm()
965 + cs)); in ddr3_write_leveling_sw_reg_dimm()
966 /* [3-0] = 0x2 - refresh, [11-8] - enable current cs */ in ddr3_write_leveling_sw_reg_dimm()
967 reg_write(REG_SDRAM_OPERATION_ADDR, reg); /* 0x1418 - SDRAM Operation Register */ in ddr3_write_leveling_sw_reg_dimm()
978 * Configure MR1 in Cs[CsNum] - write leveling on, in ddr3_write_leveling_sw_reg_dimm()
981 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Configure MR1 for current Cs: WL-on,OB-on\n"); in ddr3_write_leveling_sw_reg_dimm()
986 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw_reg_dimm()
990 * [7]=1, [12]=0 - Output Buffer and write leveling in ddr3_write_leveling_sw_reg_dimm()
993 /* 0x15D4 - DDR3 MR1 Register */ in ddr3_write_leveling_sw_reg_dimm()
995 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw_reg_dimm()
997 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
999 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_write_leveling_sw_reg_dimm()
1000 * enable current cs in ddr3_write_leveling_sw_reg_dimm()
1002 /* 0x1418 - SDRAM Operation Register */ in ddr3_write_leveling_sw_reg_dimm()
1007 /* Write leveling cs[cs] */ in ddr3_write_leveling_sw_reg_dimm()
1009 ddr3_write_leveling_single_cs(cs, freq, ratio_2to1, in ddr3_write_leveling_sw_reg_dimm()
1010 (u32 *)(res + cs), in ddr3_write_leveling_sw_reg_dimm()
1012 DEBUG_WL_FULL_C("DDR3 - Write Leveling single Cs - FAILED - Cs - ", in ddr3_write_leveling_sw_reg_dimm()
1013 (u32) cs, 1); in ddr3_write_leveling_sw_reg_dimm()
1017 /* Set TrnWLDeUpd - After each CS is done */ in ddr3_write_leveling_sw_reg_dimm()
1020 /* 0x16AC - Training Write leveling register */ in ddr3_write_leveling_sw_reg_dimm()
1024 * Debug message - Finished Write leveling cs[cs] - in ddr3_write_leveling_sw_reg_dimm()
1027 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Finished Cs - ", (u32) cs, in ddr3_write_leveling_sw_reg_dimm()
1029 DEBUG_WL_FULL_C("DDR3 - Write Leveling - The Results: 1-PUP locked, 0-PUP failed -", in ddr3_write_leveling_sw_reg_dimm()
1030 (u32) res[cs], 3); in ddr3_write_leveling_sw_reg_dimm()
1032 /* Configure MR1 in cs[cs] - write leveling off (0), output buffer off (1) */ in ddr3_write_leveling_sw_reg_dimm()
1036 /* No need to sort ODT since it is same CS */ in ddr3_write_leveling_sw_reg_dimm()
1037 /* 0x15D4 - DDR3 MR1 Register */ in ddr3_write_leveling_sw_reg_dimm()
1039 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw_reg_dimm()
1041 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
1043 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_write_leveling_sw_reg_dimm()
1044 * enable current cs in ddr3_write_leveling_sw_reg_dimm()
1046 /* 0x1418 - SDRAM Operation Register */ in ddr3_write_leveling_sw_reg_dimm()
1054 /* [2]=1 - TrnWLMode - Disable */ in ddr3_write_leveling_sw_reg_dimm()
1057 /* 0x15B8 - Training SW 2 Register */ in ddr3_write_leveling_sw_reg_dimm()
1060 /* Disable SW override - Must be in a different stage */ in ddr3_write_leveling_sw_reg_dimm()
1061 /* [0]=0 - Enable SW override */ in ddr3_write_leveling_sw_reg_dimm()
1064 /* 0x15B8 - Training SW 2 Register */ in ddr3_write_leveling_sw_reg_dimm()
1067 /* Set Output buffer-on to all CS and correct ODT values */ in ddr3_write_leveling_sw_reg_dimm()
1068 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
1069 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
1073 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw_reg_dimm()
1075 /* 0x15D0 - DDR3 MR1 Register */ in ddr3_write_leveling_sw_reg_dimm()
1077 /* Issue MRS Command to current cs */ in ddr3_write_leveling_sw_reg_dimm()
1079 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
1081 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_write_leveling_sw_reg_dimm()
1082 * enable current cs in ddr3_write_leveling_sw_reg_dimm()
1084 /* 0x1418 - SDRAM Operation Register */ in ddr3_write_leveling_sw_reg_dimm()
1103 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_sw_reg_dimm()
1109 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Finished WL procedure for all Cs\n"); in ddr3_write_leveling_sw_reg_dimm()
1117 * Args: cs - current chip select
1118 * freq - current sequence frequency
1119 * result - res array
1120 * dram_info - main struct
1124 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1, in ddr3_write_leveling_single_cs() argument
1130 max_pup_num = dram_info->num_of_total_pups; in ddr3_write_leveling_single_cs()
1134 DEBUG_WL_FULL_C("DDR3 - Write Leveling Single Cs - WL for Cs - ", in ddr3_write_leveling_single_cs()
1135 (u32) cs, 1); in ddr3_write_leveling_single_cs()
1138 case 2: in ddr3_write_leveling_single_cs()
1163 /* CS ODT Override */ in ddr3_write_leveling_single_cs()
1166 reg |= (REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA << (2 * cs)); in ddr3_write_leveling_single_cs()
1167 /* Set 0x3 - Enable ODT on the curent cs and disable on other cs */ in ddr3_write_leveling_single_cs()
1168 /* 0x1498 - SDRAM ODT Control high */ in ddr3_write_leveling_single_cs()
1171 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - ODT Asserted for current Cs\n"); in ddr3_write_leveling_single_cs()
1174 /* Delay of minimum 40 Dram clock cycles - 20 Tclk cycles */ in ddr3_write_leveling_single_cs()
1177 /* [1:0] - current cs number */ in ddr3_write_leveling_single_cs()
1178 reg = (reg_read(REG_TRAINING_WL_ADDR) & REG_TRAINING_WL_CS_MASK) | cs; in ddr3_write_leveling_single_cs()
1179 reg |= (1 << REG_TRAINING_WL_UPD_OFFS); /* [2] - trnWLCsUpd */ in ddr3_write_leveling_single_cs()
1180 /* 0x16AC - Training Write leveling register */ in ddr3_write_leveling_single_cs()
1184 ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, 0, 0); in ddr3_write_leveling_single_cs()
1187 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Current Cs\n"); in ddr3_write_leveling_single_cs()
1189 /* Drive DQS high for one cycle - All data PUPs */ in ddr3_write_leveling_single_cs()
1190 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Driving DQS high for one cycle\n"); in ddr3_write_leveling_single_cs()
1198 /* 0x16AC - Training Write leveling register */ in ddr3_write_leveling_single_cs()
1203 /* [29] - trnWLDelayExp */ in ddr3_write_leveling_single_cs()
1211 /* [28:20] - TrnWLResult */ in ddr3_write_leveling_single_cs()
1213 if (!ratio_2to1) /* Different phase options for 2:1 or 1:1 modes */ in ddr3_write_leveling_single_cs()
1218 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Shift DQS + Octet Leveling\n"); in ddr3_write_leveling_single_cs()
1224 ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, phase, in ddr3_write_leveling_single_cs()
1229 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge: Phase = "); in ddr3_write_leveling_single_cs()
1235 /* Drive DQS high for one cycle - All data PUPs */ in ddr3_write_leveling_single_cs()
1258 DEBUG_WL_FULL_C("DDR3 - Write Leveling Single Cs - Seek Edge: Results = ", in ddr3_write_leveling_single_cs()
1263 /* ECC support - bit 8 */ in ddr3_write_leveling_single_cs()
1264 pup_num = (pup == dram_info->num_of_std_pups) ? in ddr3_write_leveling_single_cs()
1266 if (dram_info->wl_val[cs][pup][S] == 0) { in ddr3_write_leveling_single_cs()
1268 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_single_cs()
1270 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_single_cs()
1278 && (dram_info->wl_val[cs][pup][S] == 0)) { in ddr3_write_leveling_single_cs()
1284 dram_info->wl_val[cs][pup][S] = 1; in ddr3_write_leveling_single_cs()
1290 /* If all locked - Break the loops - Finished */ in ddr3_write_leveling_single_cs()
1294 DEBUG_WL_S("DDR3 - Write Leveling Single Cs - Seek Edge: All Locked\n"); in ddr3_write_leveling_single_cs()
1299 /* Debug message - Print res for cs[i]: cs,PUP,Phase,Delay */ in ddr3_write_leveling_single_cs()
1300 DEBUG_WL_C("DDR3 - Write Leveling - Results for CS - ", (u32) cs, 1); in ddr3_write_leveling_single_cs()
1302 DEBUG_WL_S("DDR3 - Write Leveling - PUP: "); in ddr3_write_leveling_single_cs()
1305 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][P], 1); in ddr3_write_leveling_single_cs()
1307 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][D], 2); in ddr3_write_leveling_single_cs()
1313 DEBUG_WL_S("DDR3 - Write Leveling - ERROR - not all PUPS were locked\n"); in ddr3_write_leveling_single_cs()
1319 /* ECC support - bit 8 */ in ddr3_write_leveling_single_cs()
1320 pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup; in ddr3_write_leveling_single_cs()
1321 phase = dram_info->wl_val[cs][pup][P]; in ddr3_write_leveling_single_cs()
1322 delay = dram_info->wl_val[cs][pup][D]; in ddr3_write_leveling_single_cs()
1323 ddr3_write_pup_reg(PUP_WL_MODE, cs, pup_num, phase, delay); in ddr3_write_leveling_single_cs()
1326 /* CS ODT Override */ in ddr3_write_leveling_single_cs()
1329 /* 0x1498 - SDRAM ODT Control high */ in ddr3_write_leveling_single_cs()