Home
last modified time | relevance | path

Searched full:cr (Results 1 – 25 of 370) sorted by relevance

12345678910>>...15

/openbmc/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610.c119 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); in ddrmc_ctrl_init_ddr3()
120 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); in ddrmc_ctrl_init_ddr3()
121 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]); in ddrmc_ctrl_init_ddr3()
123 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]); in ddrmc_ctrl_init_ddr3()
125 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]); in ddrmc_ctrl_init_ddr3()
129 &ddrmr->cr[13]); in ddrmc_ctrl_init_ddr3()
132 DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]); in ddrmc_ctrl_init_ddr3()
134 DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]); in ddrmc_ctrl_init_ddr3()
136 DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]); in ddrmc_ctrl_init_ddr3()
138 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]); in ddrmc_ctrl_init_ddr3()
[all …]
H A Dddrmc-vf610-calibration.c110 while (!(readl(&ddrmr->cr[94]) & DDRMC_CR94_SWLVL_OP_DONE))
113 do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_LOAD, \
117 do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_START, \
121 do { clrsetbits_le32(&ddrmr->cr[94], DDRMC_CR94_SWLVL_EXIT, \
144 (readl(&ddrmr->cr[105]) >> DDRMC_CR105_RDLVL_DL_0_OFF) & 0xFFFF; in ddrmc_cal_dqs_to_dq()
145 u16 rdlvl_dl_1_def = readl(&ddrmr->cr[110]) & 0xFFFF; in ddrmc_cal_dqs_to_dq()
158 writel(0x40703030, &ddrmr->cr[144]); in ddrmc_cal_dqs_to_dq()
159 writel(0x40, &ddrmr->cr[145]); in ddrmc_cal_dqs_to_dq()
160 writel(0x40, &ddrmr->cr[146]); in ddrmc_cal_dqs_to_dq()
162 tmp = readl(&ddrmr->cr[144]); in ddrmc_cal_dqs_to_dq()
[all …]
/openbmc/qemu/target/hppa/
H A Dgdbstub.c43 val = env->cr[CR_SAR]; in hppa_cpu_gdb_read_register()
58 val = env->cr[CR_EIEM]; in hppa_cpu_gdb_read_register()
61 val = env->cr[CR_IIR]; in hppa_cpu_gdb_read_register()
64 val = env->cr[CR_ISR]; in hppa_cpu_gdb_read_register()
67 val = env->cr[CR_IOR]; in hppa_cpu_gdb_read_register()
70 val = env->cr[CR_IPSW]; in hppa_cpu_gdb_read_register()
97 val = env->cr[CR_RC]; in hppa_cpu_gdb_read_register()
100 val = env->cr[CR_PID1]; in hppa_cpu_gdb_read_register()
103 val = env->cr[CR_PID2]; in hppa_cpu_gdb_read_register()
106 val = env->cr[CR_SCRCCR]; in hppa_cpu_gdb_read_register()
[all …]
H A Dint_helper.c31 if (cpu->env.cr[CR_EIRR]) { in eval_interrupt()
48 return cpu->env.cr[CR_EIRR]; in io_eir_read()
60 if (hppa_is_pa20(env) && env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) { in io_eir_write()
65 env->cr[CR_EIRR] |= 1ull << le_bit; in io_eir_write()
86 env->cr[CR_EIRR] &= ~val; in HELPER()
101 env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); in hppa_cpu_do_interrupt()
106 (env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W : 0) | in hppa_cpu_do_interrupt()
115 env->cr[CR_IIASQ] = in hppa_cpu_do_interrupt()
120 env->cr[CR_IIASQ] = 0; in hppa_cpu_do_interrupt()
125 env->cr[CR_IIAOQ] = env->iaoq_f; in hppa_cpu_do_interrupt()
[all …]
/openbmc/u-boot/arch/arm/mach-at91/
H A Dmpddrc.c24 static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr) in ddr2_decodtype_is_seq() argument
30 (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)) in ddr2_decodtype_is_seq()
43 u32 ba_off, cr; in ddr2_init() local
46 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; in ddr2_init()
47 if (ddr2_decodtype_is_seq(base, mpddr_value->cr)) in ddr2_init()
48 ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; in ddr2_init()
56 writel(mpddr_value->cr, &mpddr->cr); in ddr2_init()
91 cr = readl(&mpddr->cr); in ddr2_init()
92 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); in ddr2_init()
105 cr = readl(&mpddr->cr); in ddr2_init()
[all …]
/openbmc/qemu/hw/timer/
H A Dimx_epit.c40 return "CR"; in imx_epit_reg_name()
70 if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { in imx_epit_update_int()
79 uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); in imx_epit_get_freq()
80 uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS); in imx_epit_get_freq()
94 s->cr = 0; in imx_epit_reset()
96 s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); in imx_epit_reset()
105 * The reset switches off the input clock, so even if the CR.EN is still in imx_epit_reset()
125 reg_value = s->cr; in imx_epit_read()
168 bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s); in imx_epit_update_compare_timer()
207 * of CR.OCIEN bit, as this bit affects interrupt generation only. The in imx_epit_update_compare_timer()
[all …]
H A Dimx_gpt.c27 return "CR"; in imx_gpt_reg_name()
56 VMSTATE_UINT32(cr, IMXGPTState),
143 uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); in imx_gpt_set_freq()
157 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { in imx_gpt_update_int()
188 if (!(s->cr & GPT_CR_EN)) { in imx_gpt_compute_next_timeout()
201 if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) { in imx_gpt_compute_next_timeout()
270 reg_value = s->cr; in imx_gpt_read()
332 /* Soft reset and hard reset differ only in their handling of the CR in imx_gpt_reset_common()
336 /* Clear all CR bits except those that are preserved by soft reset. */ in imx_gpt_reset_common()
337 s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN | in imx_gpt_reset_common()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmpc8536_serdes.c114 /* CR 0 */ in fsl_serdes_init()
121 /* CR 1 */ in fsl_serdes_init()
126 /* CR 2 */ in fsl_serdes_init()
133 /* CR 3 */ in fsl_serdes_init()
142 /* CR 0 */ in fsl_serdes_init()
147 /* CR 1 */ in fsl_serdes_init()
152 /* CR 2 */ in fsl_serdes_init()
157 /* CR 3 */ in fsl_serdes_init()
164 /* CR 0 */ in fsl_serdes_init()
171 /* CR 1 */ in fsl_serdes_init()
[all …]
/openbmc/u-boot/drivers/pwm/
H A Dpwm-imx.c31 u32 cr; in pwm_config() local
39 cr = PWMCR_PRESCALER(prescale) | in pwm_config()
43 writel(cr, &pwm->cr); in pwm_config()
58 setbits_le32(&pwm->cr, PWMCR_EN); in pwm_enable()
69 clrbits_le32(&pwm->cr, PWMCR_EN); in pwm_disable()
/openbmc/u-boot/drivers/mtd/
H A Dstm32_flash.c26 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK); in stm32_flash_lock()
101 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK); in flash_erase()
104 setbits_le32(&STM32_FLASH->cr, in flash_erase()
107 setbits_le32(&STM32_FLASH->cr, in flash_erase()
113 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); in flash_erase()
114 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT); in flash_erase()
119 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); in flash_erase()
135 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG); in write_buff()
146 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG); in write_buff()
/openbmc/u-boot/post/lib_powerpc/
H A Dcr.c49 ulong cr; member
64 ulong cr; member
87 ulong cr; member
236 ulong cr = cpu_post_cr_table1[i]; in cpu_post_test_cr() local
246 cpu_post_exec_11 (code, &res, cr); in cpu_post_test_cr()
248 ret = res == cr ? 0 : -1; in cpu_post_test_cr()
265 ASM_MCRXR(test->cr), in cpu_post_test_cr()
273 ret = xer == 0 && ((res << (4 * test->cr)) & 0xe0000000) == test->xer ? in cpu_post_test_cr()
295 cpu_post_exec_11 (code, &res, test->cr); in cpu_post_test_cr()
318 cpu_post_exec_11 (code, &res, test->cr); in cpu_post_test_cr()
H A Dsrawi.c23 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
99 ulong cr; in cpu_post_test_srawi() local
103 cr = 0; in cpu_post_test_srawi()
104 cpu_post_exec_21 (code, & cr, & res, test->op1); in cpu_post_test_srawi()
106 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_srawi()
116 cpu_post_exec_21 (codecr, & cr, & res, test->op1); in cpu_post_test_srawi()
119 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_srawi()
H A Drlwinm.c23 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
98 ulong cr; in cpu_post_test_rlwinm() local
102 cr = 0; in cpu_post_test_rlwinm()
103 cpu_post_exec_21 (code, & cr, & res, test->op1); in cpu_post_test_rlwinm()
105 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_rlwinm()
115 cpu_post_exec_21 (codecr, & cr, & res, test->op1); in cpu_post_test_rlwinm()
118 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_rlwinm()
H A Dtwo.c26 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
119 ulong cr; in cpu_post_test_two() local
123 cr = 0; in cpu_post_test_two()
124 cpu_post_exec_21 (code, & cr, & res, test->op); in cpu_post_test_two()
126 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_two()
136 cpu_post_exec_21 (codecr, & cr, & res, test->op); in cpu_post_test_two()
139 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_two()
H A Drlwimi.c23 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
105 ulong cr; in cpu_post_test_rlwimi() local
109 cr = 0; in cpu_post_test_rlwimi()
110 cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1); in cpu_post_test_rlwimi()
112 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_rlwimi()
122 cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1); in cpu_post_test_rlwimi()
125 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_rlwimi()
H A Dtwox.c26 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
119 ulong cr; in cpu_post_test_twox() local
123 cr = 0; in cpu_post_test_twox()
124 cpu_post_exec_21 (code, & cr, & res, test->op); in cpu_post_test_twox()
126 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_twox()
136 cpu_post_exec_21 (codecr, & cr, & res, test->op); in cpu_post_test_twox()
139 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_twox()
H A Drlwnm.c23 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
108 ulong cr; in cpu_post_test_rlwnm() local
112 cr = 0; in cpu_post_test_rlwnm()
113 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_rlwnm()
115 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_rlwnm()
125 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_rlwnm()
128 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_rlwnm()
/openbmc/u-boot/drivers/timer/
H A Dag101p_timer.c56 u32 cr; /* 0x30 */ member
79 u32 cr; in atftmr_timer_probe() local
86 cr = readl(&regs->cr); in atftmr_timer_probe()
87 cr |= (T3_ENABLE|T3_UPDOWN); in atftmr_timer_probe()
88 writel(cr, &regs->cr); in atftmr_timer_probe()
/openbmc/u-boot/drivers/spi/
H A Dzynq_spi.c41 u32 cr; /* 0x00 */ member
119 writel(confr, &regs->cr); in zynq_spi_init_hw()
145 u32 cr; in spi_cs_activate() local
155 clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK); in spi_cs_activate()
156 cr = readl(&regs->cr); in spi_cs_activate()
163 cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; in spi_cs_activate()
164 writel(cr, &regs->cr); in spi_cs_activate()
177 setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK); in spi_cs_deactivate()
286 confr = readl(&regs->cr); in zynq_spi_set_speed()
300 writel(confr, &regs->cr); in zynq_spi_set_speed()
[all …]
/openbmc/qemu/hw/display/
H A Dvga.c212 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5; in vga_precise_update_retrace_info()
213 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START]; in vga_precise_update_retrace_info()
214 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3; in vga_precise_update_retrace_info()
215 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f; in vga_precise_update_retrace_info()
217 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] | in vga_precise_update_retrace_info()
218 (((s->cr[VGA_CRTC_OVERFLOW] & 1) | in vga_precise_update_retrace_info()
219 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2; in vga_precise_update_retrace_info()
220 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] | in vga_precise_update_retrace_info()
221 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) | in vga_precise_update_retrace_info()
222 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8); in vga_precise_update_retrace_info()
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/dmalloc/dmalloc/
H A D100-use-xtools.patch46 - (ar cr conftest.a conftest.o) 2>&5
47 + (${ac_cv_prog_AR} cr conftest.a conftest.o) 2>&5
86 - ar cr $@ $?
87 + @AR@ cr $@ $?
91 - ar cr $@ $?
92 + @AR@ cr $@ $?
99 - ar cr $@ $?
100 + @AR@ cr $@ $?
107 - ar cr $@ $?
108 + @AR@ cr $@ $?
/openbmc/u-boot/arch/nds32/cpu/n1213/ag101/
H A Dtimer.c21 unsigned int cr; in timer_init() local
26 writel(0, &tmr->cr); in timer_init()
45 cr = readl(&tmr->cr); in timer_init()
47 cr |= FTTMR010_TM3_CLOCK; /* use external clock */ in timer_init()
49 cr |= FTTMR010_TM3_ENABLE; in timer_init()
50 writel(cr, &tmr->cr); in timer_init()
/openbmc/u-boot/board/keymile/km83xx/
H A Dkm83xx_i2c.c19 out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); in i2c_write_start_seq()
21 out_8(&base->cr, (I2C_CR_MEN)); in i2c_write_start_seq()
35 out_8(&base->cr, (I2C_CR_MSTA)); in i2c_make_abort()
37 out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); in i2c_make_abort()
60 out_8(&base->cr, (I2C_CR_MEN)); in i2c_make_abort()
/openbmc/u-boot/arch/m68k/cpu/mcf547x_8x/
H A Dslicetimer.c36 out_be32(&timerp->cr, 0); in __udelay()
38 out_be32(&timerp->cr, SLT_CR_TEN); in __udelay()
45 out_be32(&timerp->cr, 0); in __udelay()
67 out_be32(&timerp->cr, 0); in timer_init()
82 out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN); in timer_init()
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-daemons/tftp-hpa/files/
H A Dtftp-hpa-bug-fix-on-separated-CR-and-LF.patch4 Subject: [PATCH] tftp-hpa: bug fix on separated CR and LF
6 In ascii mode, if the CR and LF was separated into different transfer
7 blocks, LF will be just dropped instead of replacing the previous CR.
35 if (prevchar == '\r') { /* if prev char was cr */

12345678910>>...15