1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2a47a12beSStefan Roese /*
3a47a12beSStefan Roese * (C) Copyright 2002
4a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5a47a12beSStefan Roese */
6a47a12beSStefan Roese
7a47a12beSStefan Roese #include <common.h>
8a47a12beSStefan Roese
9a47a12beSStefan Roese /*
10a47a12beSStefan Roese * CPU test
11a47a12beSStefan Roese * Shift instructions: rlwinm
12a47a12beSStefan Roese *
13a47a12beSStefan Roese * The test contains a pre-built table of instructions, operands and
14a47a12beSStefan Roese * expected results. For each table entry, the test will cyclically use
15a47a12beSStefan Roese * different sets of operand registers and result registers.
16a47a12beSStefan Roese */
17a47a12beSStefan Roese
18a47a12beSStefan Roese #include <post.h>
19a47a12beSStefan Roese #include "cpu_asm.h"
20a47a12beSStefan Roese
21a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU
22a47a12beSStefan Roese
23a47a12beSStefan Roese extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
24a47a12beSStefan Roese extern ulong cpu_post_makecr (long v);
25a47a12beSStefan Roese
26a47a12beSStefan Roese static struct cpu_post_rlwinm_s
27a47a12beSStefan Roese {
28a47a12beSStefan Roese ulong cmd;
29a47a12beSStefan Roese ulong op1;
30a47a12beSStefan Roese uchar op2;
31a47a12beSStefan Roese uchar mb;
32a47a12beSStefan Roese uchar me;
33a47a12beSStefan Roese ulong res;
34a47a12beSStefan Roese } cpu_post_rlwinm_table[] =
35a47a12beSStefan Roese {
36a47a12beSStefan Roese {
37a47a12beSStefan Roese OP_RLWINM,
38a47a12beSStefan Roese 0xffff0000,
39a47a12beSStefan Roese 24,
40a47a12beSStefan Roese 16,
41a47a12beSStefan Roese 23,
42a47a12beSStefan Roese 0x0000ff00
43a47a12beSStefan Roese },
44a47a12beSStefan Roese };
45d2397817SMike Frysinger static unsigned int cpu_post_rlwinm_size = ARRAY_SIZE(cpu_post_rlwinm_table);
46a47a12beSStefan Roese
cpu_post_test_rlwinm(void)47a47a12beSStefan Roese int cpu_post_test_rlwinm (void)
48a47a12beSStefan Roese {
49a47a12beSStefan Roese int ret = 0;
50a47a12beSStefan Roese unsigned int i, reg;
51a47a12beSStefan Roese int flag = disable_interrupts();
52a47a12beSStefan Roese
53a47a12beSStefan Roese for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++)
54a47a12beSStefan Roese {
55a47a12beSStefan Roese struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i;
56a47a12beSStefan Roese
57a47a12beSStefan Roese for (reg = 0; reg < 32 && ret == 0; reg++)
58a47a12beSStefan Roese {
59a47a12beSStefan Roese unsigned int reg0 = (reg + 0) % 32;
60a47a12beSStefan Roese unsigned int reg1 = (reg + 1) % 32;
61a47a12beSStefan Roese unsigned int stk = reg < 16 ? 31 : 15;
62a47a12beSStefan Roese unsigned long code[] =
63a47a12beSStefan Roese {
64a47a12beSStefan Roese ASM_STW(stk, 1, -4),
65a47a12beSStefan Roese ASM_ADDI(stk, 1, -16),
66a47a12beSStefan Roese ASM_STW(3, stk, 8),
67a47a12beSStefan Roese ASM_STW(reg0, stk, 4),
68a47a12beSStefan Roese ASM_STW(reg1, stk, 0),
69a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8),
70a47a12beSStefan Roese ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
71a47a12beSStefan Roese ASM_STW(reg1, stk, 8),
72a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0),
73a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4),
74a47a12beSStefan Roese ASM_LWZ(3, stk, 8),
75a47a12beSStefan Roese ASM_ADDI(1, stk, 16),
76a47a12beSStefan Roese ASM_LWZ(stk, 1, -4),
77a47a12beSStefan Roese ASM_BLR,
78a47a12beSStefan Roese };
79a47a12beSStefan Roese unsigned long codecr[] =
80a47a12beSStefan Roese {
81a47a12beSStefan Roese ASM_STW(stk, 1, -4),
82a47a12beSStefan Roese ASM_ADDI(stk, 1, -16),
83a47a12beSStefan Roese ASM_STW(3, stk, 8),
84a47a12beSStefan Roese ASM_STW(reg0, stk, 4),
85a47a12beSStefan Roese ASM_STW(reg1, stk, 0),
86a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8),
87a47a12beSStefan Roese ASM_113(test->cmd, reg1, reg0, test->op2, test->mb,
88a47a12beSStefan Roese test->me) | BIT_C,
89a47a12beSStefan Roese ASM_STW(reg1, stk, 8),
90a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0),
91a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4),
92a47a12beSStefan Roese ASM_LWZ(3, stk, 8),
93a47a12beSStefan Roese ASM_ADDI(1, stk, 16),
94a47a12beSStefan Roese ASM_LWZ(stk, 1, -4),
95a47a12beSStefan Roese ASM_BLR,
96a47a12beSStefan Roese };
97a47a12beSStefan Roese ulong res;
98a47a12beSStefan Roese ulong cr;
99a47a12beSStefan Roese
100a47a12beSStefan Roese if (ret == 0)
101a47a12beSStefan Roese {
102a47a12beSStefan Roese cr = 0;
103a47a12beSStefan Roese cpu_post_exec_21 (code, & cr, & res, test->op1);
104a47a12beSStefan Roese
105a47a12beSStefan Roese ret = res == test->res && cr == 0 ? 0 : -1;
106a47a12beSStefan Roese
107a47a12beSStefan Roese if (ret != 0)
108a47a12beSStefan Roese {
109a47a12beSStefan Roese post_log ("Error at rlwinm test %d !\n", i);
110a47a12beSStefan Roese }
111a47a12beSStefan Roese }
112a47a12beSStefan Roese
113a47a12beSStefan Roese if (ret == 0)
114a47a12beSStefan Roese {
115a47a12beSStefan Roese cpu_post_exec_21 (codecr, & cr, & res, test->op1);
116a47a12beSStefan Roese
117a47a12beSStefan Roese ret = res == test->res &&
118a47a12beSStefan Roese (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
119a47a12beSStefan Roese
120a47a12beSStefan Roese if (ret != 0)
121a47a12beSStefan Roese {
122a47a12beSStefan Roese post_log ("Error at rlwinm test %d !\n", i);
123a47a12beSStefan Roese }
124a47a12beSStefan Roese }
125a47a12beSStefan Roese }
126a47a12beSStefan Roese }
127a47a12beSStefan Roese
128a47a12beSStefan Roese if (flag)
129a47a12beSStefan Roese enable_interrupts();
130a47a12beSStefan Roese
131a47a12beSStefan Roese return ret;
132a47a12beSStefan Roese }
133a47a12beSStefan Roese
134a47a12beSStefan Roese #endif
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