CAS (full) in projects: openbmc - OpenGrok search results

Searched full:cas (Results 1 – 25 of 219) sorted by relevance

/openbmc/u-boot/board/sunxi/
H A D	dram_timings_sun4i.h	`5 .cas = 6, 11 .cas = 6, 17 .cas = 6, 23 .cas = 7, 29 .cas = 7, 35 .cas = 7, 41 .cas = 7, 47 .cas = 7, 53 .cas = 7, 59 .cas = 7, [all …]`
/openbmc/u-boot/include/dt-bindings/memory/
H A D	mpc83xx-sdram.h	`63 #define CASLAT_20 0x3 /* CAS latency = 2.0 / 64 #define CASLAT_25 0x4 / CAS latency = 2.5 / 65 #define CASLAT_30 0x5 / CAS latency = 3.0 / 66 #define CASLAT_35 0x6 / CAS latency = 3.5 / 67 #define CASLAT_40 0x7 / CAS latency = 4.0 / 68 #define CASLAT_45 0x8 / CAS latency = 4.5 / 69 #define CASLAT_50 0x9 / CAS latency = 5.0 / 70 #define CASLAT_55 0xa / CAS latency = 5.5 / 71 #define CASLAT_60 0xb / CAS latency = 6.0 / 72 #define CASLAT_65 0xc / CAS latency = 6.5 */ [all …]`
/openbmc/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	uncore-memory.json	3 …"BriefDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum … 7 …licDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of … 21 …"BriefDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum… 25 …icDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of … 30 …"BriefDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum … 34 …licDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of … 48 …"BriefDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum… 52 …icDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of … 78 "BriefDescription": "Read CAS command sent to DRAM", 85 "BriefDescription": "Write CAS command sent to DRAM",
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A D	mv_ddr_spd.h	171 unsigned char byte_20; /* cas latencies supported, first byte / 172 unsigned char byte_21; / cas latencies supported, second byte / 173 unsigned char byte_22; / cas latencies supported, third byte / 174 unsigned char byte_23; / cas latencies supported, fourth byte / 175 unsigned char byte_24; / min cas latency time (t aa min), mtb / 176 unsigned char byte_25; / min ras to cas delay time (t rcd min), mtb / 205 unsigned char byte_40; / min cas to cas delay time (t ccd_l min), same bank group, mtb / 226 / fine offset for min cas to cas delay time (t ccd_l min), same bank group, ftb / 235 unsigned char byte_122; / fine offset for min ras to cas delay time (t rcd min), ftb / 236 unsigned char byte_123; / fine offset for min cas latency time (t aa min), ftb */
H A D	mv_ddr_topology.c	`109 /* update cas write latency (cwl) / in mv_ddr_topology_map_update() 112 printf("mv_ddr: unsupported cas write latency value found\n"); in mv_ddr_topology_map_update() 117 / update cas latency (cl) / in mv_ddr_topology_map_update() 121 printf("mv_ddr: unsupported cas latency value found\n"); in mv_ddr_topology_map_update() 126 / set cas and cas-write latencies per speed bin, if they unset */ in mv_ddr_topology_map_update()`
H A D	mv_ddr_topology.h	`117 MV_DDR_TAA_MIN, /* min cas latency time (t aa min) / 120 MV_DDR_TRCD_MIN, / min ras to cas delay time (t rcd min) / 126 MV_DDR_TCCD_L_MIN, / min cas to cas delay time (t ccd_l min), same bank group */`
/openbmc/u-boot/drivers/ddr/fsl/
H A D	lc_common_dimm_params.c	31 /* compute the common CAS latency supported between slots / in compute_cas_latency() 50 / determine the acutal cas latency / in compute_cas_latency() 52 / check if the dimms support the CAS latency / in compute_cas_latency() 58 we must verify that this CAS latency value does not in compute_cas_latency() 63 printf("The chosen cas latency %d is too large\n", in compute_cas_latency() 91 * Compute a CAS latency suitable for all DIMMs in compute_cas_latency() 94 * CAS latency defined by all DIMMs. in compute_cas_latency() 98 * Step 1: find CAS latency common to all DIMMs using bitwise in compute_cas_latency() 124 * Step 2: check each common CAS latency against tCK of each in compute_cas_latency() 134 /* Check if this CAS latency will work on all DIMMs at tCK. */ in compute_cas_latency() [all …]
H A D	ddr2_dimm_params.c	143 * CAS latency given the DRAM clock period. The SPD only 144 * defines at most 3 CAS latencies. Typically the slower in 145 * frequency the DIMM runs at, the shorter its CAS latency can. 147 * it may be able to run at a CAS latency shorter than the 148 * shortest SPD-defined CAS latency. 150 * If a CAS latency is not found, 0 is returned. 160 * CAS latency de-rating based upon values JEDEC Standard No. 79-2C 287 * Compute CAS latencies defined by SPD in ddr_compute_dimm_parameters() 300 /* Compute CAS latencies below that defined by SPD */ in ddr_compute_dimm_parameters()
H A D	ddr1_dimm_params.c	162 * CAS latency given the DRAM clock period. The SPD only 163 * defines at most 3 CAS latencies. Typically the slower in 164 * frequency the DIMM runs at, the shorter its CAS latency can be. 166 * it may be able to run at a CAS latency shorter than the 167 * shortest SPD-defined CAS latency. 169 * If a CAS latency is not found, 0 is returned. 179 * CAS latency de-rating based upon values JEDEC Standard No. 79-E 288 * Compute CAS latencies defined by SPD in ddr_compute_dimm_parameters() 301 /* Compute CAS latencies below that defined by SPD */ in ddr_compute_dimm_parameters()
/openbmc/linux/drivers/net/ethernet/sun/
H A D	cassini.c	229 static void cas_set_link_modes(struct cas cp); 231 static inline void cas_lock_tx(struct cas cp) in cas_lock_tx() 249 struct cas xxxcp = (cp); \ 254 static inline void cas_unlock_tx(struct cas cp) in cas_unlock_tx() 264 struct cas xxxcp = (cp); \ 269 static void cas_disable_irq(struct cas cp, const int ring) in cas_disable_irq() 302 static inline void cas_mask_intr(struct cas cp) in cas_mask_intr() 310 static void cas_enable_irq(struct cas cp, const int ring) in cas_enable_irq() 339 static inline void cas_unmask_intr(struct cas cp) in cas_unmask_intr() 347 static inline void cas_entropy_gather(struct cas cp) in cas_entropy_gather() [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	uncore-memory.json	7 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu… 17 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p… 27 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 36 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 41 "BriefDescription": "All DRAM CAS commands issued", 45 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.", 50 "BriefDescription": "All DRAM read CAS commands issued (including underfills)", 54 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu… 63 …s : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both … 77 "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)", [all …]
/openbmc/linux/arch/parisc/kernel/
H A D	syscall.S	568 Implementing 32bit CAS as an atomic operation: 577 EAGAIN - CAS is busy, ldcw failed, try again. 581 r28 == 1 - CAS is busy. lock contended. 582 r28 == 2 - CAS is busy. ldcw failed. 583 r28 == 3 - CAS is busy. page fault. 596 * the 64-bit LWS CAS returns ENOSYS. 676 New CAS implementation which uses pointers and variable size 678 while performing CAS. The lock only protects the value at %r26. 688 EAGAIN - CAS is busy, ldcw failed, try again. 692 r28 == 1 - CAS is busy. lock contended. [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	uncore-memory.json	1499 …n up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate… 1508 …n up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate… 1517 …n up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate… 1526 …n up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate… 1535 …n up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate… 1544 …n up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate… 1553 …n up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate… 1562 …n up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate… 1571 …n up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate… 1580 …n up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate… [all …]
/openbmc/u-boot/include/
H A D	ddr_spd.h	32 unsigned char cas_lat; /* 18 CAS# Latencies Supported / 44 unsigned char trcd; / 29 Min RAS to CAS Delay (tRCD) / 95 unsigned char cas_lat; / 18 CAS# Latencies Supported / 106 unsigned char trcd; / 29 Min RAS to CAS Delay (tRCD) / 193 unsigned char caslat_lsb; / 14 CAS Latencies Supported, 195 unsigned char caslat_msb; /* 15 CAS Latencies Supported, 197 unsigned char taa_min; /* 16 Min CAS Latency Time / 199 unsigned char trcd_min; / 18 Min RAS# to CAS# Delay Time / 313 uint8_t caslat_b1; / 20 CAS latencies, 1st byte / 314 uint8_t caslat_b2; / 21 CAS latencies, 2nd byte */ [all …]
H A D	fsl_ddr_dimm_params.h	`52 int taa_ps; /* minimum CAS latency time / 64 / SPD-defined CAS latencies / 69 unsigned int caslat_lowest_derated; / Derated CAS latency */`
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	uncore-memory.json	7 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per … 17 …"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory ch… 27 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 36 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 45 … up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Sele… 58 "BriefDescription": "CAS command issued by 2 cycle bypass", 60 "EventName": "UNC_M_BYP_CMDS.CAS", 74 "BriefDescription": "All DRAM CAS Commands issued", 78 …"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory ch… 83 "BriefDescription": "All DRAM Read CAS Commands issued (including underfills)", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	uncore-memory.json	`71 "BriefDescription": "CAS All", 79 "BriefDescription": "CAS Reads", 87 "BriefDescription": "CAS Writes",`
/openbmc/openbmc/poky/meta/files/common-licenses/
H A D	CECILL-1.0	36 Logiciel: désigne le logiciel sous sa forme de Code Objet et/ou de Code Source et le cas &#233… 38 Logiciel Initial: désigne le Logiciel sous sa forme de Code Source et de Code Objet et le cas … 124 et que, dans le cas où seul le Code Objet du Logiciel est redistribué, le Licencié p… 136 et que, dans le cas où seul le Code Objet du Logiciel Modifié est redistribué, le Li… 144 Dans le cas où le Logiciel, Modifié ou non, est intégré à un code soumis a… 146 Dans le cas où le Logiciel Modifié intègre un code soumis aux dispositions de la lic… 172 … intellectuelle du Titulaire et/ou des Contributeurs et à prendre, le cas échéant, … 176 7.1. Le Contrat n’oblige en aucun cas le Concédant à la réalisation de prestat… 200 …3;fense. Cette aide technique et juridique est déterminée au cas par cas entre le Conc&#… 204 10.1. En cas de manquement par le Licencié aux obligations mises à sa charge par le Contr… [all …]
H A D	CECILL-C	36 Logiciel: désigne le logiciel sous sa forme de Code Objet et/ou de Code Source et le cas &#233… 38 …el sous sa forme de Code Source et éventuellement de Code Objet et le cas échéant s… 90 …cessifs qui utiliseraient, exploiteraient ou modifieraient le Logiciel. En cas de cession de ces b… 122 et que, dans le cas où seul le Code Objet du Logiciel est redistribué, le Licencié p… 134 et que, dans le cas où seul le code objet du Logiciel Modifié est redistribué, le Li… 138 …its sur le Logiciel telles que définies à l`article 6.4. Dans le cas où la cré… 172 …du Titulaire et/ou des Contributeurs sur le Logiciel et à prendre, le cas échéant, … 176 7.1 Le Contrat n`oblige en aucun cas le Concédant à la réalisation de prestations d`… 200 …3;fense. Cette aide technique et juridique est déterminée au cas par cas entre le Conc&#… 204 10.1 En cas de manquement par le Licencié aux obligations mises à sa charge par le Contra… [all …]
H A D	CECILL-2.0	36 Logiciel: désigne le logiciel sous sa forme de Code Objet et/ou de Code Source et le cas &#233… 38 …el sous sa forme de Code Source et éventuellement de Code Objet et le cas échéant s… 94 …cessifs qui utiliseraient, exploiteraient ou modifieraient le Logiciel. En cas de cession de ces b… 126 et que, dans le cas où seul le Code Objet du Logiciel est redistribué, le Licencié p… 138 et que, dans le cas où seul le code objet du Logiciel Modifié est redistribué, le Li… 174 …du Titulaire et/ou des Contributeurs sur le Logiciel et à prendre, le cas échéant, … 178 7.1 Le Contrat n`oblige en aucun cas le Concédant à la réalisation de prestations d`… 202 …3;fense. Cette aide technique et juridique est déterminée au cas par cas entre le Conc&#… 206 10.1 En cas de manquement par le Licencié aux obligations mises à sa charge par le Contra… 214 …ance d`exécution du Contrat qui serait dû à un cas de force majeure, un cas fortuit… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	uncore-memory.json	7 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 16 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 21 "BriefDescription": "All DRAM CAS commands issued", 25 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.", 30 "BriefDescription": "All DRAM read CAS commands issued (including underfills)", 34 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu… 43 …s : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both … 57 "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)", 61 …": "Counts the total number of DRAM Read CAS commands issued on this channel. This includes both … 66 "BriefDescription": "DRAM underfill read CAS commands issued", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	uncore-memory.json	7 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per … 17 …"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory ch… 27 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 36 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 45 … up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Sele… 58 "BriefDescription": "CAS command issued by 2 cycle bypass", 60 "EventName": "UNC_M_BYP_CMDS.CAS", 74 "BriefDescription": "All DRAM CAS Commands issued", 78 …"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory ch… 83 "BriefDescription": "All DRAM Read CAS Commands issued (including underfills)", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	uncore-memory.json	7 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 16 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 25 … up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate… 38 "BriefDescription": "CAS command issued by 2 cycle bypass", 40 "EventName": "UNC_M_BYP_CMDS.CAS", 58 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS command… 67 …n": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on … 76 …ds; Counts the total number or DRAM Read CAS commands issued on this channel. This includes both … 81 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM", 98 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM", [all …]
/openbmc/linux/arch/sparc/include/asm/
H A D	cmpxchg_64.h	`13 __asm__ __volatile__("cas [%2], %3, %0" in __cmpxchg_u32() 28 " cas [%4], %2, %0\n" in xchg32() 65 * Use 4 byte cas instruction to achieve 2 byte xchg. Main logic 126 * Use 4 byte cas instruction to achieve 1 byte cmpxchg. Main logic`
/openbmc/qemu/target/mips/tcg/sysemu/
H A D	lcsr_helper.c	`13 #define GET_MEMTXATTRS(cas) \ argument 14 ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})`

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