1[
2    {
3        "BriefDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels).",
4        "EventCode": "0xff",
5        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
6        "PerPkg": "1",
7        "PublicDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.",
8        "UMask": "0x20",
9        "Unit": "imc_free_running_0"
10    },
11    {
12        "BriefDescription": "Counts every read and write request entering the Memory Controller 0.",
13        "EventCode": "0xff",
14        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
15        "PerPkg": "1",
16        "PublicDescription": "Counts every read and write request entering the Memory Controller 0 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW.",
17        "UMask": "0x10",
18        "Unit": "imc_free_running_0"
19    },
20    {
21        "BriefDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels).",
22        "EventCode": "0xff",
23        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
24        "PerPkg": "1",
25        "PublicDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels).  Each CAS commands can be for 32B or 64B of data.",
26        "UMask": "0x30",
27        "Unit": "imc_free_running_0"
28    },
29    {
30        "BriefDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels).",
31        "EventCode": "0xff",
32        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
33        "PerPkg": "1",
34        "PublicDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.",
35        "UMask": "0x20",
36        "Unit": "imc_free_running_1"
37    },
38    {
39        "BriefDescription": "Counts every read and write request entering the Memory Controller 1.",
40        "EventCode": "0xff",
41        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
42        "PerPkg": "1",
43        "PublicDescription": "Counts every read and write request entering the Memory Controller 1 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW.",
44        "UMask": "0x10",
45        "Unit": "imc_free_running_1"
46    },
47    {
48        "BriefDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels).",
49        "EventCode": "0xff",
50        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
51        "PerPkg": "1",
52        "PublicDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels).  Each CAS commands can be for 32B or 64B of data.",
53        "UMask": "0x30",
54        "Unit": "imc_free_running_1"
55    },
56    {
57        "BriefDescription": "ACT command for a read request sent to DRAM",
58        "EventCode": "0x24",
59        "EventName": "UNC_M_ACT_COUNT_RD",
60        "PerPkg": "1",
61        "Unit": "iMC"
62    },
63    {
64        "BriefDescription": "ACT command sent to DRAM",
65        "EventCode": "0x26",
66        "EventName": "UNC_M_ACT_COUNT_TOTAL",
67        "PerPkg": "1",
68        "Unit": "iMC"
69    },
70    {
71        "BriefDescription": "ACT command for a write request sent to DRAM",
72        "EventCode": "0x25",
73        "EventName": "UNC_M_ACT_COUNT_WR",
74        "PerPkg": "1",
75        "Unit": "iMC"
76    },
77    {
78        "BriefDescription": "Read CAS command sent to DRAM",
79        "EventCode": "0x22",
80        "EventName": "UNC_M_CAS_COUNT_RD",
81        "PerPkg": "1",
82        "Unit": "iMC"
83    },
84    {
85        "BriefDescription": "Write CAS command sent to DRAM",
86        "EventCode": "0x23",
87        "EventName": "UNC_M_CAS_COUNT_WR",
88        "PerPkg": "1",
89        "Unit": "iMC"
90    },
91    {
92        "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration",
93        "EventCode": "0x28",
94        "EventName": "UNC_M_PRE_COUNT_IDLE",
95        "PerPkg": "1",
96        "Unit": "iMC"
97    },
98    {
99        "BriefDescription": "PRE command sent to DRAM for a read/write request",
100        "EventCode": "0x27",
101        "EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
102        "PerPkg": "1",
103        "Unit": "iMC"
104    },
105    {
106        "BriefDescription": "Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data.",
107        "EventCode": "0x3A",
108        "EventName": "UNC_M_RD_DATA",
109        "PerPkg": "1",
110        "Unit": "iMC"
111    },
112    {
113        "BriefDescription": "Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data.",
114        "EventCode": "0x3C",
115        "EventName": "UNC_M_TOTAL_DATA",
116        "PerPkg": "1",
117        "Unit": "iMC"
118    },
119    {
120        "BriefDescription": "Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data.",
121        "EventCode": "0x3B",
122        "EventName": "UNC_M_WR_DATA",
123        "PerPkg": "1",
124        "Unit": "iMC"
125    }
126]
127