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/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
[all …]
H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
[all …]
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
13 # bit 3-0: MPPSel0 2, NF_IO[2]
14 # bit 7-4: MPPSel1 2, NF_IO[3]
15 # bit 12-8: MPPSel2 2, NF_IO[4]
16 # bit 15-12: MPPSel3 2, NF_IO[5]
17 # bit 19-16: MPPSel4 1, NF_IO[6]
18 # bit 23-20: MPPSel5 1, NF_IO[7]
19 # bit 27-24: MPPSel6 1, SYSRST_O
20 # bit 31-28: MPPSel7 0, GPO[7]
[all …]
/openbmc/u-boot/drivers/sound/
H A Dmax98088.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * max98088.h -- MAX98088 ALSA SoC Audio driver
91 /* MAX98088 Registers Bit Fields */
97 #define M98088_DAI_MAS BIT(7)
98 #define M98088_DAI_WCI BIT(6)
99 #define M98088_DAI_BCI BIT(5)
100 #define M98088_DAI_DLY BIT(4)
101 #define M98088_DAI_TDM BIT(2)
102 #define M98088_DAI_FSW BIT(1)
103 #define M98088_DAI_WS BIT(0)
[all …]
H A Dmax98090.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * max98090.h -- MAX98090 ALSA SoC Audio driver
66 /* MAX98090 Registers Bit Fields */
71 #define M98090_SWRESET_MASK BIT(7)
76 #define M98090_SR_96K_MASK BIT(5)
79 #define M98090_SR_32K_MASK BIT(4)
82 #define M98090_SR_48K_MASK BIT(3)
85 #define M98090_SR_44K1_MASK BIT(2)
88 #define M98090_SR_16K_MASK BIT(1)
91 #define M98090_SR_8K_MASK BIT(0)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(11)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(10)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(9)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(8)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(7)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(15)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(14)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(13)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(12)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(11)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_SWC_CLEAR_IF BIT(6)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(5)
23 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(4)
24 #define ICPU_GENERAL_CTRL_IF_MASTER_DIS BIT(3)
25 #define ICPU_GENERAL_CTRL_IF_MASTER_SPI_ENA BIT(2)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk322x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
19 * bit width in address, eg:
20 * 8 banks using 3 bit to address,
21 * 2 cs using 1 bit to address.
33 * For of-platdata, which would otherwise convert this into two
34 * byte-swapped integers. With a size of 9 bytes, this struct will
35 * appear in of-platdata as a byte array.
48 u32 reserved0[(0x40 - 0x10) / 4];
54 u32 reserved1[(0x60 - 0x54) / 4];
58 u32 reserved2[(0x7c - 0x6c) / 4];
[all …]
H A Dlvds_rk3288.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7)
11 #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6)
12 #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5)
13 #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4)
14 #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3)
15 #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2)
16 #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1)
17 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
20 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5)
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Ddenali.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2014 Altera Corporation <www.altera.com>
4 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
15 #define DEVICE_RESET__BANK(bank) BIT(bank)
18 #define TRANSFER_SPARE_REG__FLAG BIT(0)
33 #define RB_PIN_ENABLED__BANK(bank) BIT(bank)
36 #define MULTIPLANE_OPERATION__FLAG BIT(0)
39 #define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
42 #define COPYBACK_DISABLE__FLAG BIT(0)
45 #define CACHE_WRITE_ENABLE__FLAG BIT(0)
[all …]
/openbmc/u-boot/drivers/tee/optee/
H A Doptee_smc.h1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2015-2018, Linaro Limited
9 #include <linux/arm-smccc.h>
14 * https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/include/sm/optee_smc.h
35 * Normal cached memory (write-back), shareable for SMP systems and not
43 * 32-bit registers.
51 * 65cb6b93-af0c-4617-8ed6-644a8d1140f8
82 * Used by non-secure world to figure out which Trusted OS is installed.
85 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
95 * Used by non-secure world to figure out which version of the Trusted OS
[all …]
/openbmc/u-boot/drivers/spi/
H A Datmel_spi.h18 #define ATMEL_SPI_CR_SPIEN BIT(0)
19 #define ATMEL_SPI_CR_SPIDIS BIT(1)
20 #define ATMEL_SPI_CR_SWRST BIT(7)
21 #define ATMEL_SPI_CR_LASTXFER BIT(24)
24 #define ATMEL_SPI_MR_MSTR BIT(0)
25 #define ATMEL_SPI_MR_PS BIT(1)
26 #define ATMEL_SPI_MR_PCSDEC BIT(2)
27 #define ATMEL_SPI_MR_FDIV BIT(3)
28 #define ATMEL_SPI_MR_MODFDIS BIT(4)
29 #define ATMEL_SPI_MR_WDRBT BIT(5)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dsdram_ast2600.h1 /* SPDX-License-Identifier: GPL-2.0+ */
20 #define REQ_PRI_PCIE_BUS2_RW 7
41 #define MCR30_RESET_DLL_DELAY_EN BIT(4)
44 #define MCR30_SET_MODE_REG BIT(0)
54 #define MCR34_ODT_AUTO_ON BIT(9)
55 #define MCR34_ODT_EN BIT(8)
56 #define MCR34_RESETN_DIS BIT(7)
57 #define MCR34_MREQI_DIS BIT(6)
58 #define MCR34_MREQ_BYPASS_DIS BIT(5)
59 #define MCR34_RGAP_CTRL_EN BIT(4)
[all …]
/openbmc/qemu/include/hw/usb/
H A Ddwc2-regs.h1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
7 * hw.h - DesignWare HS OTG Controller hardware definitions
9 * Copyright 2004-2013 Synopsys, Inc.
20 * 3. The names of the above-listed copyright holders may not be used
48 #define GOTGCTL_CHIRPEN BIT(27)
51 #define GOTGCTL_OTGVER BIT(20)
52 #define GOTGCTL_BSESVLD BIT(19)
53 #define GOTGCTL_ASESVLD BIT(18)
54 #define GOTGCTL_DBNC_SHORT BIT(17)
55 #define GOTGCTL_CONID_B BIT(16)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-owl/
H A Dclk_s900.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 #include <clk-uclass.h>
20 #define CMU_PDBGDIV_8 7
23 #define CMU_PERDIV_8 7
32 #define CMU_APBCLK_DIV BIT(8)
33 #define CMU_NOCCLK_SRC BIT(7)
34 #define CMU_AHBCLK_DIV BIT(4)
36 #define CMU_CORECLK_CPLL BIT(1)
37 #define CMU_CORECLK_HOSC BIT(0)
40 #define CMU_COREPLL_EN BIT(9)
[all …]
/openbmc/qemu/include/hw/ssi/
H A Dpnv_spi_regs.h6 * SPDX-License-Identifier: GPL-2.0-or-later
17 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) argument
18 #define PPC_BIT8(bit) (0x80 >> (bit)) argument
19 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
20 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
21 #define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
31 #define SPI_CTR_CFG_N1 PPC_BITMASK(0, 7)
80 #define SPI_STS_TDR PPC_BITMASK(5, 7)
86 * status register. It's a 12 bit field so we will represent it as three
91 * Status reg bits 16-27 -> field bits 0-11
[all …]
/openbmc/phosphor-power/phosphor-regulators/src/actions/
H A Di2c_write_bit_action.hpp8 * http://www.apache.org/licenses/LICENSE-2.0
31 * Writes a bit to a device register. Communicates with the device directly
39 // Specify which compiler-generated methods we want
54 * @param position Bit position. Must be in the range 0-7. Bit 0 is the
55 * least significant bit.
56 * @param value Bit value to write. Must be 0 or 1.
61 if (position > 7)
64 "Invalid bit position: " +
71 "Invalid bit value: " +
79 * Writes a bit to a device register using the I2C interface.
[all …]
H A Di2c_compare_bit_action.hpp8 * http://www.apache.org/licenses/LICENSE-2.0
31 * Compares a bit in a device register to a value. Communicates with the device
39 // Specify which compiler-generated methods we want
54 * @param position Bit position. Must be in the range 0-7. Bit 0 is the
55 * least significant bit.
56 * @param value Expected bit value. Must be 0 or 1.
61 if (position > 7)
64 "Invalid bit position: " +
71 "Invalid bit value: " +
79 * Compares a bit in a device register to a value using the I2C interface.
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
342 #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2)
368 #define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30)
369 #define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31)
381 #define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30)
[all …]
/openbmc/u-boot/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define STM32F4_RCC_AHB1_GPIOH 7
34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
42 #define STM32F4_RCC_AHB2_OTGFS 7
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
62 #define STM32F4_RCC_APB1_TIM13 7
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dscu_info.c1 // SPDX-License-Identifier: GPL-2.0+
21 SOC_ID("AST2600-A0", 0x0500030305000303),
22 SOC_ID("AST2600-A1", 0x0501030305010303),
23 SOC_ID("AST2620-A1", 0x0501020305010203),
24 SOC_ID("AST2600-A2", 0x0502030305010303),
25 SOC_ID("AST2620-A2", 0x0502020305010203),
26 SOC_ID("AST2605-A2", 0x0502010305010103),
27 SOC_ID("AST2600-A3", 0x0503030305030303),
28 SOC_ID("AST2620-A3", 0x0503020305030203),
29 SOC_ID("AST2605-A3", 0x0503010305030103),
[all …]
/openbmc/u-boot/drivers/net/
H A Dpic32_eth.h1 /* SPDX-License-Identifier: GPL-2.0+ */
49 struct pic32_mii_regs mii; /* 0x280 - 0x2d0 */
58 #define ETHCON_BUFCDEC BIT(0)
59 #define ETHCON_RXEN BIT(8)
60 #define ETHCON_TXRTS BIT(9)
61 #define ETHCON_ON BIT(15)
68 #define ETHSTAT_BUSY BIT(7)
72 #define ETHRXFC_BCEN BIT(0)
73 #define ETHRXFC_MCEN BIT(1)
74 #define ETHRXFC_UCEN BIT(3)
[all …]

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