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/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
10 * information contained in the core-isa.h header file.
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
25 /* Copyright (c) 1999-2020 Tensilica Inc.
49 /*----------------------------------------------------------------------
51 ----------------------------------------------------------------------*/
55 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
117 #define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */
118 #define XCHAL_CA_WRITEBACK 7 /* cache enabled (write-back) mode */
[all …]
/openbmc/linux/arch/x86/kernel/cpu/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
6 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
33 #define LVL_3 4
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
63 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
65 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
66 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
[all …]
H A Dintel.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <asm/intel-family.h>
67 * Processors which have self-snooping capability can handle conflicting
75 switch (c->x86_vfm) { in check_memory_type_self_snoop_errata()
107 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
109 switch (c->x86_vfm) { in probe_xeon_phi_r3mwait()
131 * - https://newsroom.intel.com/wp-conten
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/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
10 * information contained in the core-isa.h header file.
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
25 /* Copyright (c) 1999-2010 Tensilica Inc.
49 /*----------------------------------------------------------------------
51 ----------------------------------------------------------------------*/
54 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
112 #define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
113 #define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */
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/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S1 /* SPDX-License-Identifier: GPL-2.0+ */
19 * Flush the whole D-cache.
21 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
23 * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
38 blt skip @ skip if no cache, or just i-cache
43 add r2, r2, #4 @ add 4 (line length offset)
45 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
46 clz r5, r4 @ find bit position of way size increment
52 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
54 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
28 compatible = "arm,armv7-timer";
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H A Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
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/openbmc/linux/arch/xtensa/include/asm/
H A Dtlbflush.h6 * Copyright (C) 2001 - 2013 Tensilica Inc.
17 #define ITLB_ARF_WAYS 4
18 #define DTLB_ARF_WAYS 4
21 #define DTLB_HIT_BIT 4
27 * - flush_tlb_all() flushes all processes TLB entries
28 * - flush_tlb_mm(mm) flushes the specified mm context TLB entries
29 * - flush_tlb_page(vma, page) flushes a single page
30 * - flush_tlb_range(vma, vmaddr, end) flushes a range of pages
130 static inline void write_dtlb_entry (pte_t entry, int way) in write_dtlb_entry() argument
133 : : "r" (way), "r" (entry) ); in write_dtlb_entry()
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/openbmc/linux/arch/arc/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
175 * Flush the entire MM for userland. The fastest way is to move to Next ASID
185 if (atomic_read(&mm->mm_users) == 0) in local_flush_tlb_mm()
189 * - Move to a new ASID, but only if the mm is still wired in in local_flush_tlb_mm()
190 * (Android Binder ended up calling this for vma->mm != tsk->mm, in local_flush_tlb_mm()
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/openbmc/linux/arch/mips/mm/
H A Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
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/openbmc/u-boot/doc/
H A DREADME.N12137 - 16-/32-bit mixable instruction format.
8 - 32 general-purpose 32-bit registers.
9 - 8-stage pipeline.
10 - Dynamic branch prediction.
11 - 32/64/128/256 BTB.
12 - Return address stack (RAS).
13 - Vector interrupts for internal/external.
15 - 3 HW-level nested interruptions.
16 - User and super-user mode support.
17 - Memory-mapped I/O.
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/openbmc/linux/arch/powerpc/mm/nohash/
H A Dtlb_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
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/openbmc/u-boot/arch/powerpc/include/asm/
H A De300.h15 * Hardware Implementation-Dependent Register 0 (HID0)
77 * Hardware Implementation-Dependent Register 2 (HID2)
84 #define HID2_IWLCK_001 0x00002000 /* way 0 locked */
85 #define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
86 #define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
87 #define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
88 #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
89 #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dsubcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
37 * ------------|------------------
39 * 2-way split | 2
40 * 4-way split | 4
46 * ----------------------------
48 * ----------------------------
49 * Thread | 0 1 2 3 4 5 6 7 |
50 * ----------------------------
52 * 2-way split:
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/openbmc/linux/arch/x86/crypto/
H A Dblowfish-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 .file "blowfish-x86_64-asm.S"
15 #define s0 ((16 + 2) * 4)
16 #define s1 ((16 + 2 + (1 * 256)) * 4)
17 #define s2 ((16 + 2 + (2 * 256)) * 4)
18 #define s3 ((16 + 2 + (3 * 256)) * 4)
57 * 1-way blowfish
64 movl s0(CTX,RT0,4), RT0d; \
65 addl s1(CTX,RT1,4), RT0d; \
69 xorl s2(CTX,RT1,4), RT0d; \
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H A Dtwofish_glue_3way.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Glue Code for 3-way parallel assembler optimized version of Twofish
24 return twofish_setkey(&tfm->base, key, keylen); in twofish_setkey_skcipher()
47 ECB_WALK_START(req, TF_BLOCK_SIZE, -1); in ecb_encrypt()
55 ECB_WALK_START(req, TF_BLOCK_SIZE, -1); in ecb_decrypt()
63 CBC_WALK_START(req, TF_BLOCK_SIZE, -1); in cbc_encrypt()
70 CBC_WALK_START(req, TF_BLOCK_SIZE, -1); in cbc_decrypt()
79 .base.cra_driver_name = "ecb-twofish-3way",
91 .base.cra_driver_name = "cbc-twofish-3way",
115 * On Atom, twofish-3way is slower than original assembler in is_blacklisted_cpu()
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/openbmc/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
31 #define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS)
45 #define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) argument
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/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dyuv-formats.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _yuv-formats:
12 *color difference* signals, this way the green component can be
16 color in a way compatible with existing receivers a new signal carrier
29 direction are possible, common factors are 1 (no subsampling), 2 and 4, with
33 - `4:4:4`: No subsampling
34 - `4:2:2`: Horizontal subsampling by 2, no vertical subsampling
35 - `4:2:0`: Horizontal subsampling by 2, vertical subsampling by 2
36 - `4:1:1`: Horizontal subsampling by 4, no vertical subsampling
37 - `4:1:0`: Horizontal subsampling by 4, vertical subsampling by 4
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
74 #define CP0_BRCM_MODE_ClkRATIO_MASK (7 << 4)
85 #define BRCM_ZSC_RBUS_ADDR_MAPPING_REG0 4 << 3
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
137 /* sets per way = (64<<IS) */
146 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
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/openbmc/qemu/target/xtensa/
H A Dmmu_helper.c2 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 #include "qemu/qemu-print.h"
33 #include "exec/helper-proto.h"
34 #include "qemu/host-utils.h"
35 #include "exec/exec-all.h"
36 #include "exec/page-protection.h"
67 * only the side-effects (ie any MMU or other exception) in HELPER()
76 if (v != env->sregs[RASID]) { in HELPER()
77 env->sregs[RASID] = v; in HELPER()
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/openbmc/linux/arch/sh/mm/
H A Dcache-sh2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh2.c
23 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
24 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_wback_region()
25 & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
28 int way; in sh2__flush_wback_region() local
29 for (way = 0; way < 4; way++) { in sh2__flush_wback_region()
30 unsigned long data = __raw_readl(addr | (way << 12)); in sh2__flush_wback_region()
33 __raw_writel(data, addr | (way << 12)); in sh2__flush_wback_region()
44 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_purge_region()
[all …]
/openbmc/linux/arch/arm/mm/
H A Dcache-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7.S
15 #include <asm/hardware/cache-b15-rac.h>
17 #include "proc-macros.S"
19 .arch armv7-a
51 mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...]
53 moveq r1, #1 @ r1 needs value > 0 even if only 1 way
56 add r2, r2, #4 @ SetShift
64 subs r0, r0, #1 @ Set--
66 subs r3, r3, r1 @ Way--
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/openbmc/qemu/target/ppc/
H A Dmmu_common.c4 * Copyright (c) 2003-2007 Jocelyn Mayer
25 #include "mmu-hash64.h"
26 #include "mmu-hash32.h"
27 #include "exec/exec-all.h"
28 #include "exec/page-protection.h"
31 #include "qemu/error-report.h"
32 #include "qemu/qemu-print.h"
34 #include "mmu-book3s-v3.h"
35 #include "mmu-radix64.h"
36 #include "mmu-booke.h"
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/openbmc/qemu/docs/
H A Dqdev-device-use.txt1 = How to convert to -device & friends =
7 -device parameter bus.
10 where this address can be configured, devices provide a bus-specific
16 SCSI scsi-id %u
19 virtio-serial-bus nr %u
20 ccid-bus slot %u
23 Example: device i440FX-pcihost is on the root bus, and provides a PCI
24 bus named pci.0. To put a FOO device into its slot 4, use -device
25 FOO,bus=/i440FX-pcihost/pci.0,addr=4. The abbreviated form bus=pci.0
45 The new way keeps the parts separate: you create the host part with
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/openbmc/qemu/docs/specs/
H A Divshmem-spec.rst2 Device Specification for Inter-VM shared memory device
5 The Inter-VM shared memory device (ivshmem) is designed to share a
27 --------
31 - BAR0 holds device registers (256 Byte MMIO)
32 - BAR1 holds MSI-X table and PBA (only ivshmem-doorbell)
33 - BAR2 maps the shared memory object
37 - If you only need the shared memory part, BAR2 suffices. This way,
41 - If you additionally need the capability for peers to interrupt each
50 IVPosition register (described below) to become non-negative before
57 --------------------
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