1*79bc0fb5SMax Filippov /* 2*79bc0fb5SMax Filippov * xtensa/config/core-matmap.h -- Memory access and translation mapping 3*79bc0fb5SMax Filippov * parameters (CHAL) of the Xtensa processor core configuration. 4*79bc0fb5SMax Filippov * 5*79bc0fb5SMax Filippov * If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes 6*79bc0fb5SMax Filippov * this file) for more details. 7*79bc0fb5SMax Filippov * 8*79bc0fb5SMax Filippov * In the Xtensa processor products released to date, all parameters 9*79bc0fb5SMax Filippov * defined in this file are derivable (at least in theory) from 10*79bc0fb5SMax Filippov * information contained in the core-isa.h header file. 11*79bc0fb5SMax Filippov * In particular, the following core configuration parameters are relevant: 12*79bc0fb5SMax Filippov * XCHAL_HAVE_CACHEATTR 13*79bc0fb5SMax Filippov * XCHAL_HAVE_MIMIC_CACHEATTR 14*79bc0fb5SMax Filippov * XCHAL_HAVE_XLT_CACHEATTR 15*79bc0fb5SMax Filippov * XCHAL_HAVE_PTP_MMU 16*79bc0fb5SMax Filippov * XCHAL_ITLB_ARF_ENTRIES_LOG2 17*79bc0fb5SMax Filippov * XCHAL_DTLB_ARF_ENTRIES_LOG2 18*79bc0fb5SMax Filippov * XCHAL_DCACHE_IS_WRITEBACK 19*79bc0fb5SMax Filippov * XCHAL_ICACHE_SIZE (presence of I-cache) 20*79bc0fb5SMax Filippov * XCHAL_DCACHE_SIZE (presence of D-cache) 21*79bc0fb5SMax Filippov * XCHAL_HW_VERSION_MAJOR 22*79bc0fb5SMax Filippov * XCHAL_HW_VERSION_MINOR 23*79bc0fb5SMax Filippov */ 24*79bc0fb5SMax Filippov 25*79bc0fb5SMax Filippov /* Copyright (c) 1999-2020 Tensilica Inc. 26*79bc0fb5SMax Filippov 27*79bc0fb5SMax Filippov Permission is hereby granted, free of charge, to any person obtaining 28*79bc0fb5SMax Filippov a copy of this software and associated documentation files (the 29*79bc0fb5SMax Filippov "Software"), to deal in the Software without restriction, including 30*79bc0fb5SMax Filippov without limitation the rights to use, copy, modify, merge, publish, 31*79bc0fb5SMax Filippov distribute, sublicense, and/or sell copies of the Software, and to 32*79bc0fb5SMax Filippov permit persons to whom the Software is furnished to do so, subject to 33*79bc0fb5SMax Filippov the following conditions: 34*79bc0fb5SMax Filippov 35*79bc0fb5SMax Filippov The above copyright notice and this permission notice shall be included 36*79bc0fb5SMax Filippov in all copies or substantial portions of the Software. 37*79bc0fb5SMax Filippov 38*79bc0fb5SMax Filippov THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39*79bc0fb5SMax Filippov EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 40*79bc0fb5SMax Filippov MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 41*79bc0fb5SMax Filippov IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 42*79bc0fb5SMax Filippov CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 43*79bc0fb5SMax Filippov TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 44*79bc0fb5SMax Filippov SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 45*79bc0fb5SMax Filippov 46*79bc0fb5SMax Filippov #ifndef XTENSA_CONFIG_CORE_MATMAP_H 47*79bc0fb5SMax Filippov #define XTENSA_CONFIG_CORE_MATMAP_H 48*79bc0fb5SMax Filippov 49*79bc0fb5SMax Filippov /*---------------------------------------------------------------------- 50*79bc0fb5SMax Filippov CACHE (MEMORY ACCESS) ATTRIBUTES 51*79bc0fb5SMax Filippov ----------------------------------------------------------------------*/ 52*79bc0fb5SMax Filippov 53*79bc0fb5SMax Filippov 54*79bc0fb5SMax Filippov 55*79bc0fb5SMax Filippov /* Cache Attribute encodings -- lists of access modes for each cache attribute: */ 56*79bc0fb5SMax Filippov #define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ 57*79bc0fb5SMax Filippov XTHAL_FAM_BYPASS XCHAL_SEP \ 58*79bc0fb5SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 59*79bc0fb5SMax Filippov XTHAL_FAM_BYPASS XCHAL_SEP \ 60*79bc0fb5SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 61*79bc0fb5SMax Filippov XTHAL_FAM_CACHED XCHAL_SEP \ 62*79bc0fb5SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 63*79bc0fb5SMax Filippov XTHAL_FAM_CACHED XCHAL_SEP \ 64*79bc0fb5SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 65*79bc0fb5SMax Filippov XTHAL_FAM_CACHED XCHAL_SEP \ 66*79bc0fb5SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 67*79bc0fb5SMax Filippov XTHAL_FAM_CACHED XCHAL_SEP \ 68*79bc0fb5SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 69*79bc0fb5SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 70*79bc0fb5SMax Filippov XTHAL_FAM_EXCEPTION XCHAL_SEP \ 71*79bc0fb5SMax Filippov XTHAL_FAM_EXCEPTION 72*79bc0fb5SMax Filippov #define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \ 73*79bc0fb5SMax Filippov XTHAL_LAM_BYPASSG XCHAL_SEP \ 74*79bc0fb5SMax Filippov XTHAL_LAM_BYPASSG XCHAL_SEP \ 75*79bc0fb5SMax Filippov XTHAL_LAM_BYPASSG XCHAL_SEP \ 76*79bc0fb5SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 77*79bc0fb5SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 78*79bc0fb5SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 79*79bc0fb5SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 80*79bc0fb5SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 81*79bc0fb5SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 82*79bc0fb5SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 83*79bc0fb5SMax Filippov XTHAL_LAM_CACHED XCHAL_SEP \ 84*79bc0fb5SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 85*79bc0fb5SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 86*79bc0fb5SMax Filippov XTHAL_LAM_EXCEPTION XCHAL_SEP \ 87*79bc0fb5SMax Filippov XTHAL_LAM_EXCEPTION 88*79bc0fb5SMax Filippov #define XCHAL_SCA_LIST XTHAL_SAM_EXCEPTION XCHAL_SEP \ 89*79bc0fb5SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 90*79bc0fb5SMax Filippov XTHAL_SAM_BYPASS XCHAL_SEP \ 91*79bc0fb5SMax Filippov XTHAL_SAM_BYPASS XCHAL_SEP \ 92*79bc0fb5SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 93*79bc0fb5SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 94*79bc0fb5SMax Filippov XTHAL_SAM_WRITEBACK XCHAL_SEP \ 95*79bc0fb5SMax Filippov XTHAL_SAM_WRITEBACK XCHAL_SEP \ 96*79bc0fb5SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 97*79bc0fb5SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 98*79bc0fb5SMax Filippov XTHAL_SAM_WRITETHRU XCHAL_SEP \ 99*79bc0fb5SMax Filippov XTHAL_SAM_WRITETHRU XCHAL_SEP \ 100*79bc0fb5SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 101*79bc0fb5SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 102*79bc0fb5SMax Filippov XTHAL_SAM_EXCEPTION XCHAL_SEP \ 103*79bc0fb5SMax Filippov XTHAL_SAM_EXCEPTION 104*79bc0fb5SMax Filippov 105*79bc0fb5SMax Filippov #define XCHAL_CA_R (0xC0 | 0x40000000) 106*79bc0fb5SMax Filippov #define XCHAL_CA_RX (0xD0 | 0x40000000) 107*79bc0fb5SMax Filippov #define XCHAL_CA_RW (0xE0 | 0x40000000) 108*79bc0fb5SMax Filippov #define XCHAL_CA_RWX (0xF0 | 0x40000000) 109*79bc0fb5SMax Filippov 110*79bc0fb5SMax Filippov /* 111*79bc0fb5SMax Filippov * Specific encoded cache attribute values of general interest. 112*79bc0fb5SMax Filippov * If a specific cache mode is not available, the closest available 113*79bc0fb5SMax Filippov * one is returned instead (eg. writethru instead of writeback, 114*79bc0fb5SMax Filippov * bypass instead of writethru). 115*79bc0fb5SMax Filippov */ 116*79bc0fb5SMax Filippov #define XCHAL_CA_BYPASS 3 /* cache disabled (bypassed) mode */ 117*79bc0fb5SMax Filippov #define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */ 118*79bc0fb5SMax Filippov #define XCHAL_CA_WRITEBACK 7 /* cache enabled (write-back) mode */ 119*79bc0fb5SMax Filippov #define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */ 120*79bc0fb5SMax Filippov #define XCHAL_CA_WRITEBACK_NOALLOC 7 /* cache enabled (write-back no-allocate) mode */ 121*79bc0fb5SMax Filippov #define XCHAL_CA_BYPASS_RX 1 /* cache disabled (bypassed) mode (no write) */ 122*79bc0fb5SMax Filippov #define XCHAL_CA_WRITETHRU_RX 9 /* cache enabled (write-through) mode (no write) */ 123*79bc0fb5SMax Filippov #define XCHAL_CA_WRITEBACK_RX 5 /* cache enabled (write-back) mode (no write) */ 124*79bc0fb5SMax Filippov #define XCHAL_CA_WRITEBACK_NOALLOC_RX 5 /* cache enabled (write-back no-allocate) mode (no write) */ 125*79bc0fb5SMax Filippov #define XCHAL_CA_BYPASS_RW 2 /* cache disabled (bypassed) mode (no exec) */ 126*79bc0fb5SMax Filippov #define XCHAL_CA_WRITETHRU_RW 10 /* cache enabled (write-through) mode (no exec) */ 127*79bc0fb5SMax Filippov #define XCHAL_CA_WRITEBACK_RW 6 /* cache enabled (write-back) mode (no exec) */ 128*79bc0fb5SMax Filippov #define XCHAL_CA_WRITEBACK_NOALLOC_RW 6 /* cache enabled (write-back no-allocate) mode (no exec) */ 129*79bc0fb5SMax Filippov #define XCHAL_CA_BYPASS_R 0 /* cache disabled (bypassed) mode (no exec, no write) */ 130*79bc0fb5SMax Filippov #define XCHAL_CA_WRITETHRU_R 8 /* cache enabled (write-through) mode (no exec, no write) */ 131*79bc0fb5SMax Filippov #define XCHAL_CA_WRITEBACK_R 4 /* cache enabled (write-back) mode (no exec, no write) */ 132*79bc0fb5SMax Filippov #define XCHAL_CA_WRITEBACK_NOALLOC_R 4 /* cache enabled (write-back no-allocate) mode (no exec, no write) */ 133*79bc0fb5SMax Filippov #define XCHAL_CA_ILLEGAL 12 /* no access allowed (all cause exceptions) mode */ 134*79bc0fb5SMax Filippov 135*79bc0fb5SMax Filippov /*---------------------------------------------------------------------- 136*79bc0fb5SMax Filippov MMU 137*79bc0fb5SMax Filippov ----------------------------------------------------------------------*/ 138*79bc0fb5SMax Filippov 139*79bc0fb5SMax Filippov /* 140*79bc0fb5SMax Filippov * General notes on MMU parameters. 141*79bc0fb5SMax Filippov * 142*79bc0fb5SMax Filippov * Terminology: 143*79bc0fb5SMax Filippov * ASID = address-space ID (acts as an "extension" of virtual addresses) 144*79bc0fb5SMax Filippov * VPN = virtual page number 145*79bc0fb5SMax Filippov * PPN = physical page number 146*79bc0fb5SMax Filippov * CA = encoded cache attribute (access modes) 147*79bc0fb5SMax Filippov * TLB = translation look-aside buffer (term is stretched somewhat here) 148*79bc0fb5SMax Filippov * I = instruction (fetch accesses) 149*79bc0fb5SMax Filippov * D = data (load and store accesses) 150*79bc0fb5SMax Filippov * way = each TLB (ITLB and DTLB) consists of a number of "ways" 151*79bc0fb5SMax Filippov * that simultaneously match the virtual address of an access; 152*79bc0fb5SMax Filippov * a TLB successfully translates a virtual address if exactly 153*79bc0fb5SMax Filippov * one way matches the vaddr; if none match, it is a miss; 154*79bc0fb5SMax Filippov * if multiple match, one gets a "multihit" exception; 155*79bc0fb5SMax Filippov * each way can be independently configured in terms of number of 156*79bc0fb5SMax Filippov * entries, page sizes, which fields are writable or constant, etc. 157*79bc0fb5SMax Filippov * set = group of contiguous ways with exactly identical parameters 158*79bc0fb5SMax Filippov * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE 159*79bc0fb5SMax Filippov * from the page table and storing it in one of the auto-refill ways; 160*79bc0fb5SMax Filippov * if this PTE load also misses, a miss exception is posted for s/w. 161*79bc0fb5SMax Filippov * min-wired = a "min-wired" way can be used to map a single (minimum-sized) 162*79bc0fb5SMax Filippov * page arbitrarily under program control; it has a single entry, 163*79bc0fb5SMax Filippov * is non-auto-refill (some other way(s) must be auto-refill), 164*79bc0fb5SMax Filippov * all its fields (VPN, PPN, ASID, CA) are all writable, and it 165*79bc0fb5SMax Filippov * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current 166*79bc0fb5SMax Filippov * restriction is that this be the only page size it supports). 167*79bc0fb5SMax Filippov * 168*79bc0fb5SMax Filippov * TLB way entries are virtually indexed. 169*79bc0fb5SMax Filippov * TLB ways that support multiple page sizes: 170*79bc0fb5SMax Filippov * - must have all writable VPN and PPN fields; 171*79bc0fb5SMax Filippov * - can only use one page size at any given time (eg. setup at startup), 172*79bc0fb5SMax Filippov * selected by the respective ITLBCFG or DTLBCFG special register, 173*79bc0fb5SMax Filippov * whose bits n*4+3 .. n*4 index the list of page sizes for way n 174*79bc0fb5SMax Filippov * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); 175*79bc0fb5SMax Filippov * this list may be sparse for auto-refill ways because auto-refill 176*79bc0fb5SMax Filippov * ways have independent lists of supported page sizes sharing a 177*79bc0fb5SMax Filippov * common encoding with PTE entries; the encoding is the index into 178*79bc0fb5SMax Filippov * this list; unsupported sizes for a given way are zero in the list; 179*79bc0fb5SMax Filippov * selecting unsupported sizes results in undefine hardware behaviour; 180*79bc0fb5SMax Filippov * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). 181*79bc0fb5SMax Filippov */ 182*79bc0fb5SMax Filippov 183*79bc0fb5SMax Filippov #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ 184*79bc0fb5SMax Filippov #define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */ 185*79bc0fb5SMax Filippov #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ 186*79bc0fb5SMax Filippov #define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ 187*79bc0fb5SMax Filippov #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */ 188*79bc0fb5SMax Filippov #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */ 189*79bc0fb5SMax Filippov 190*79bc0fb5SMax Filippov 191*79bc0fb5SMax Filippov /*** Instruction TLB: ***/ 192*79bc0fb5SMax Filippov 193*79bc0fb5SMax Filippov #define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */ 194*79bc0fb5SMax Filippov #define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */ 195*79bc0fb5SMax Filippov #define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */ 196*79bc0fb5SMax Filippov #define XCHAL_ITLB_SETS 7 /* number of sets (groups of ways with identical settings) */ 197*79bc0fb5SMax Filippov 198*79bc0fb5SMax Filippov /* Way set to which each way belongs: */ 199*79bc0fb5SMax Filippov #define XCHAL_ITLB_WAY0_SET 0 200*79bc0fb5SMax Filippov #define XCHAL_ITLB_WAY1_SET 1 201*79bc0fb5SMax Filippov #define XCHAL_ITLB_WAY2_SET 2 202*79bc0fb5SMax Filippov #define XCHAL_ITLB_WAY3_SET 3 203*79bc0fb5SMax Filippov #define XCHAL_ITLB_WAY4_SET 4 204*79bc0fb5SMax Filippov #define XCHAL_ITLB_WAY5_SET 5 205*79bc0fb5SMax Filippov #define XCHAL_ITLB_WAY6_SET 6 206*79bc0fb5SMax Filippov 207*79bc0fb5SMax Filippov /* Ways sets that are used by hardware auto-refill (ARF): */ 208*79bc0fb5SMax Filippov #define XCHAL_ITLB_ARF_SETS 4 /* number of auto-refill sets */ 209*79bc0fb5SMax Filippov #define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */ 210*79bc0fb5SMax Filippov #define XCHAL_ITLB_ARF_SET1 1 /* index of n'th auto-refill set */ 211*79bc0fb5SMax Filippov #define XCHAL_ITLB_ARF_SET2 2 /* index of n'th auto-refill set */ 212*79bc0fb5SMax Filippov #define XCHAL_ITLB_ARF_SET3 3 /* index of n'th auto-refill set */ 213*79bc0fb5SMax Filippov 214*79bc0fb5SMax Filippov /* Way sets that are "min-wired" (see terminology comment above): */ 215*79bc0fb5SMax Filippov #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ 216*79bc0fb5SMax Filippov 217*79bc0fb5SMax Filippov 218*79bc0fb5SMax Filippov /* ITLB way set 0 (group of ways 0 thru 0): */ 219*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ 220*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ 221*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 222*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 223*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 224*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ 225*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ 226*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 227*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 228*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 229*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 230*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 231*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 232*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 233*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 234*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 235*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 236*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 237*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 238*79bc0fb5SMax Filippov 239*79bc0fb5SMax Filippov /* ITLB way set 1 (group of ways 1 thru 1): */ 240*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_WAY 1 /* index of first way in this way set */ 241*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */ 242*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 243*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 244*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 245*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_PAGESIZES 1 /* number of supported page sizes in this way */ 246*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */ 247*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 248*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 249*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 250*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 251*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 252*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 253*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 254*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 255*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 256*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 257*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 258*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 259*79bc0fb5SMax Filippov 260*79bc0fb5SMax Filippov /* ITLB way set 2 (group of ways 2 thru 2): */ 261*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_WAY 2 /* index of first way in this way set */ 262*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */ 263*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 264*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 265*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 266*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */ 267*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */ 268*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 269*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 270*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 271*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 272*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 273*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 274*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 275*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 276*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 277*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 278*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 279*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 280*79bc0fb5SMax Filippov 281*79bc0fb5SMax Filippov /* ITLB way set 3 (group of ways 3 thru 3): */ 282*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_WAY 3 /* index of first way in this way set */ 283*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */ 284*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 285*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 286*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 287*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */ 288*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */ 289*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 290*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 291*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 292*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 293*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 294*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 295*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 296*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 297*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 298*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 299*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 300*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 301*79bc0fb5SMax Filippov 302*79bc0fb5SMax Filippov /* ITLB way set 4 (group of ways 4 thru 4): */ 303*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_WAY 4 /* index of first way in this way set */ 304*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_WAYS 1 /* number of (contiguous) ways in this way set */ 305*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 306*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 307*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 308*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_PAGESIZES 4 /* number of supported page sizes in this way */ 309*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_PAGESZ_BITS 2 /* number of bits to encode the page size */ 310*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */ 311*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */ 312*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP; 313*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 314*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 315*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 316*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 317*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 318*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 319*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 320*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 321*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 322*79bc0fb5SMax Filippov 323*79bc0fb5SMax Filippov /* ITLB way set 5 (group of ways 5 thru 5): */ 324*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_WAY 5 /* index of first way in this way set */ 325*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_WAYS 1 /* number of (contiguous) ways in this way set */ 326*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 327*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 328*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 329*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_PAGESIZES 2 /* number of supported page sizes in this way */ 330*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_PAGESZ_BITS 1 /* number of bits to encode the page size */ 331*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */ 332*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */ 333*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_PAGESZ_LOG2_LIST 27 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; 334*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 335*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 336*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 337*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 338*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 339*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 340*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 341*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 342*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 343*79bc0fb5SMax Filippov /* Reset ASID values for each entry of ITLB way set 5 (because SET5_ASID_RESET is non-zero): */ 344*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E0_ASID_RESET 0x00 345*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E1_ASID_RESET 0x00 346*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E2_ASID_RESET 0x00 347*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E3_ASID_RESET 0x00 348*79bc0fb5SMax Filippov /* Reset VPN values for each entry of ITLB way set 5 (because SET5_VPN_RESET is non-zero): */ 349*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E0_VPN_RESET 0x00000000 350*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E1_VPN_RESET 0x00000000 351*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E2_VPN_RESET 0x00000000 352*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E3_VPN_RESET 0x00000000 353*79bc0fb5SMax Filippov /* Reset PPN values for each entry of ITLB way set 5 (because SET5_PPN_RESET is non-zero): */ 354*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E0_PPN_RESET 0x00000000 355*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E1_PPN_RESET 0x00000000 356*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E2_PPN_RESET 0x00000000 357*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET5_E3_PPN_RESET 0x00000000 358*79bc0fb5SMax Filippov 359*79bc0fb5SMax Filippov /* ITLB way set 6 (group of ways 6 thru 6): */ 360*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_WAY 6 /* index of first way in this way set */ 361*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_WAYS 1 /* number of (contiguous) ways in this way set */ 362*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ 363*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_ENTRIES 8 /* number of entries in this way (always a power of 2) */ 364*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 365*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_PAGESIZES 2 /* number of supported page sizes in this way */ 366*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_PAGESZ_BITS 1 /* number of bits to encode the page size */ 367*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */ 368*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ 369*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_PAGESZ_LOG2_LIST 29 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; 370*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 371*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 372*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 373*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 374*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 375*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 376*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 377*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 378*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 379*79bc0fb5SMax Filippov /* Reset ASID values for each entry of ITLB way set 6 (because SET6_ASID_RESET is non-zero): */ 380*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E0_ASID_RESET 0x01 381*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E1_ASID_RESET 0x01 382*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E2_ASID_RESET 0x01 383*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E3_ASID_RESET 0x01 384*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E4_ASID_RESET 0x01 385*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E5_ASID_RESET 0x01 386*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E6_ASID_RESET 0x01 387*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E7_ASID_RESET 0x01 388*79bc0fb5SMax Filippov /* Reset VPN values for each entry of ITLB way set 6 (because SET6_VPN_RESET is non-zero): */ 389*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E0_VPN_RESET 0x00000000 390*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E1_VPN_RESET 0x20000000 391*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E2_VPN_RESET 0x40000000 392*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E3_VPN_RESET 0x60000000 393*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E4_VPN_RESET 0x80000000 394*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E5_VPN_RESET 0xA0000000 395*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E6_VPN_RESET 0xC0000000 396*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E7_VPN_RESET 0xE0000000 397*79bc0fb5SMax Filippov /* Reset PPN values for each entry of ITLB way set 6 (because SET6_PPN_RESET is non-zero): */ 398*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E0_PPN_RESET 0x00000000 399*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E1_PPN_RESET 0x20000000 400*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E2_PPN_RESET 0x40000000 401*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E3_PPN_RESET 0x60000000 402*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E4_PPN_RESET 0x80000000 403*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E5_PPN_RESET 0xA0000000 404*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E6_PPN_RESET 0xC0000000 405*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E7_PPN_RESET 0xE0000000 406*79bc0fb5SMax Filippov /* Reset CA values for each entry of ITLB way set 6 (because SET6_CA_RESET is non-zero): */ 407*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E0_CA_RESET 0x03 408*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E1_CA_RESET 0x03 409*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E2_CA_RESET 0x03 410*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E3_CA_RESET 0x03 411*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E4_CA_RESET 0x03 412*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E5_CA_RESET 0x03 413*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E6_CA_RESET 0x03 414*79bc0fb5SMax Filippov #define XCHAL_ITLB_SET6_E7_CA_RESET 0x03 415*79bc0fb5SMax Filippov 416*79bc0fb5SMax Filippov 417*79bc0fb5SMax Filippov /*** Data TLB: ***/ 418*79bc0fb5SMax Filippov 419*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */ 420*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */ 421*79bc0fb5SMax Filippov #define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */ 422*79bc0fb5SMax Filippov #define XCHAL_DTLB_SETS 10 /* number of sets (groups of ways with identical settings) */ 423*79bc0fb5SMax Filippov 424*79bc0fb5SMax Filippov /* Way set to which each way belongs: */ 425*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY0_SET 0 426*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY1_SET 1 427*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY2_SET 2 428*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY3_SET 3 429*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY4_SET 4 430*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY5_SET 5 431*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY6_SET 6 432*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY7_SET 7 433*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY8_SET 8 434*79bc0fb5SMax Filippov #define XCHAL_DTLB_WAY9_SET 9 435*79bc0fb5SMax Filippov 436*79bc0fb5SMax Filippov /* Ways sets that are used by hardware auto-refill (ARF): */ 437*79bc0fb5SMax Filippov #define XCHAL_DTLB_ARF_SETS 4 /* number of auto-refill sets */ 438*79bc0fb5SMax Filippov #define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */ 439*79bc0fb5SMax Filippov #define XCHAL_DTLB_ARF_SET1 1 /* index of n'th auto-refill set */ 440*79bc0fb5SMax Filippov #define XCHAL_DTLB_ARF_SET2 2 /* index of n'th auto-refill set */ 441*79bc0fb5SMax Filippov #define XCHAL_DTLB_ARF_SET3 3 /* index of n'th auto-refill set */ 442*79bc0fb5SMax Filippov 443*79bc0fb5SMax Filippov /* Way sets that are "min-wired" (see terminology comment above): */ 444*79bc0fb5SMax Filippov #define XCHAL_DTLB_MINWIRED_SETS 3 /* number of "min-wired" sets */ 445*79bc0fb5SMax Filippov #define XCHAL_DTLB_MINWIRED_SET0 7 /* index of n'th "min-wired" set */ 446*79bc0fb5SMax Filippov #define XCHAL_DTLB_MINWIRED_SET1 8 /* index of n'th "min-wired" set */ 447*79bc0fb5SMax Filippov #define XCHAL_DTLB_MINWIRED_SET2 9 /* index of n'th "min-wired" set */ 448*79bc0fb5SMax Filippov 449*79bc0fb5SMax Filippov 450*79bc0fb5SMax Filippov /* DTLB way set 0 (group of ways 0 thru 0): */ 451*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ 452*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ 453*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 454*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 455*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 456*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ 457*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ 458*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 459*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 460*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 461*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 462*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 463*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 464*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 465*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 466*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 467*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 468*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 469*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 470*79bc0fb5SMax Filippov 471*79bc0fb5SMax Filippov /* DTLB way set 1 (group of ways 1 thru 1): */ 472*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_WAY 1 /* index of first way in this way set */ 473*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */ 474*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 475*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 476*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 477*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_PAGESIZES 1 /* number of supported page sizes in this way */ 478*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */ 479*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 480*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 481*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 482*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 483*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 484*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 485*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 486*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 487*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 488*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 489*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 490*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 491*79bc0fb5SMax Filippov 492*79bc0fb5SMax Filippov /* DTLB way set 2 (group of ways 2 thru 2): */ 493*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_WAY 2 /* index of first way in this way set */ 494*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */ 495*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 496*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 497*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 498*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */ 499*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */ 500*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 501*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 502*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 503*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 504*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 505*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 506*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 507*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 508*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 509*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 510*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 511*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 512*79bc0fb5SMax Filippov 513*79bc0fb5SMax Filippov /* DTLB way set 3 (group of ways 3 thru 3): */ 514*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_WAY 3 /* index of first way in this way set */ 515*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */ 516*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 517*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 518*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 519*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */ 520*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */ 521*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 522*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 523*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 524*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 525*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 526*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 527*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 528*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 529*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 530*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 531*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 532*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 533*79bc0fb5SMax Filippov 534*79bc0fb5SMax Filippov /* DTLB way set 4 (group of ways 4 thru 4): */ 535*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_WAY 4 /* index of first way in this way set */ 536*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_WAYS 1 /* number of (contiguous) ways in this way set */ 537*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 538*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 539*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 540*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_PAGESIZES 4 /* number of supported page sizes in this way */ 541*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_PAGESZ_BITS 2 /* number of bits to encode the page size */ 542*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */ 543*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */ 544*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP; 545*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 546*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 547*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 548*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 549*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 550*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 551*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 552*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 553*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 554*79bc0fb5SMax Filippov 555*79bc0fb5SMax Filippov /* DTLB way set 5 (group of ways 5 thru 5): */ 556*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_WAY 5 /* index of first way in this way set */ 557*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_WAYS 1 /* number of (contiguous) ways in this way set */ 558*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ 559*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_ENTRIES 4 /* number of entries in this way (always a power of 2) */ 560*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 561*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_PAGESIZES 2 /* number of supported page sizes in this way */ 562*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_PAGESZ_BITS 1 /* number of bits to encode the page size */ 563*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */ 564*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */ 565*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_PAGESZ_LOG2_LIST 27 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; 566*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 567*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 568*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 569*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 570*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 571*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 572*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 573*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 574*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 575*79bc0fb5SMax Filippov /* Reset ASID values for each entry of DTLB way set 5 (because SET5_ASID_RESET is non-zero): */ 576*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E0_ASID_RESET 0x00 577*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E1_ASID_RESET 0x00 578*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E2_ASID_RESET 0x00 579*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E3_ASID_RESET 0x00 580*79bc0fb5SMax Filippov /* Reset VPN values for each entry of DTLB way set 5 (because SET5_VPN_RESET is non-zero): */ 581*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E0_VPN_RESET 0x00000000 582*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E1_VPN_RESET 0x00000000 583*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E2_VPN_RESET 0x00000000 584*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E3_VPN_RESET 0x00000000 585*79bc0fb5SMax Filippov /* Reset PPN values for each entry of DTLB way set 5 (because SET5_PPN_RESET is non-zero): */ 586*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E0_PPN_RESET 0x00000000 587*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E1_PPN_RESET 0x00000000 588*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E2_PPN_RESET 0x00000000 589*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET5_E3_PPN_RESET 0x00000000 590*79bc0fb5SMax Filippov 591*79bc0fb5SMax Filippov /* DTLB way set 6 (group of ways 6 thru 6): */ 592*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_WAY 6 /* index of first way in this way set */ 593*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_WAYS 1 /* number of (contiguous) ways in this way set */ 594*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ 595*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_ENTRIES 8 /* number of entries in this way (always a power of 2) */ 596*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 597*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_PAGESIZES 2 /* number of supported page sizes in this way */ 598*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_PAGESZ_BITS 1 /* number of bits to encode the page size */ 599*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */ 600*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ 601*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_PAGESZ_LOG2_LIST 29 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; 602*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 603*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 604*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 605*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 606*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 607*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 608*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 609*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 610*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 611*79bc0fb5SMax Filippov /* Reset ASID values for each entry of DTLB way set 6 (because SET6_ASID_RESET is non-zero): */ 612*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E0_ASID_RESET 0x01 613*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E1_ASID_RESET 0x01 614*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E2_ASID_RESET 0x01 615*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E3_ASID_RESET 0x01 616*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E4_ASID_RESET 0x01 617*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E5_ASID_RESET 0x01 618*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E6_ASID_RESET 0x01 619*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E7_ASID_RESET 0x01 620*79bc0fb5SMax Filippov /* Reset VPN values for each entry of DTLB way set 6 (because SET6_VPN_RESET is non-zero): */ 621*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E0_VPN_RESET 0x00000000 622*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E1_VPN_RESET 0x20000000 623*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E2_VPN_RESET 0x40000000 624*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E3_VPN_RESET 0x60000000 625*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E4_VPN_RESET 0x80000000 626*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E5_VPN_RESET 0xA0000000 627*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E6_VPN_RESET 0xC0000000 628*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E7_VPN_RESET 0xE0000000 629*79bc0fb5SMax Filippov /* Reset PPN values for each entry of DTLB way set 6 (because SET6_PPN_RESET is non-zero): */ 630*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E0_PPN_RESET 0x00000000 631*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E1_PPN_RESET 0x20000000 632*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E2_PPN_RESET 0x40000000 633*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E3_PPN_RESET 0x60000000 634*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E4_PPN_RESET 0x80000000 635*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E5_PPN_RESET 0xA0000000 636*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E6_PPN_RESET 0xC0000000 637*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E7_PPN_RESET 0xE0000000 638*79bc0fb5SMax Filippov /* Reset CA values for each entry of DTLB way set 6 (because SET6_CA_RESET is non-zero): */ 639*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E0_CA_RESET 0x03 640*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E1_CA_RESET 0x03 641*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E2_CA_RESET 0x03 642*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E3_CA_RESET 0x03 643*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E4_CA_RESET 0x03 644*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E5_CA_RESET 0x03 645*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E6_CA_RESET 0x03 646*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET6_E7_CA_RESET 0x03 647*79bc0fb5SMax Filippov 648*79bc0fb5SMax Filippov /* DTLB way set 7 (group of ways 7 thru 7): */ 649*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_WAY 7 /* index of first way in this way set */ 650*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_WAYS 1 /* number of (contiguous) ways in this way set */ 651*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_ENTRIES_LOG2 0 /* log2(number of entries in this way) */ 652*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_ENTRIES 1 /* number of entries in this way (always a power of 2) */ 653*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 654*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_PAGESIZES 1 /* number of supported page sizes in this way */ 655*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_PAGESZ_BITS 0 /* number of bits to encode the page size */ 656*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 657*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 658*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 659*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 660*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 661*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 662*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 663*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 664*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 665*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 666*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 667*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET7_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 668*79bc0fb5SMax Filippov 669*79bc0fb5SMax Filippov /* DTLB way set 8 (group of ways 8 thru 8): */ 670*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_WAY 8 /* index of first way in this way set */ 671*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_WAYS 1 /* number of (contiguous) ways in this way set */ 672*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_ENTRIES_LOG2 0 /* log2(number of entries in this way) */ 673*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_ENTRIES 1 /* number of entries in this way (always a power of 2) */ 674*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 675*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_PAGESIZES 1 /* number of supported page sizes in this way */ 676*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_PAGESZ_BITS 0 /* number of bits to encode the page size */ 677*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 678*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 679*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 680*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 681*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 682*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 683*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 684*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 685*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 686*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 687*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 688*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET8_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 689*79bc0fb5SMax Filippov 690*79bc0fb5SMax Filippov /* DTLB way set 9 (group of ways 9 thru 9): */ 691*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_WAY 9 /* index of first way in this way set */ 692*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_WAYS 1 /* number of (contiguous) ways in this way set */ 693*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_ENTRIES_LOG2 0 /* log2(number of entries in this way) */ 694*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_ENTRIES 1 /* number of entries in this way (always a power of 2) */ 695*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ 696*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_PAGESIZES 1 /* number of supported page sizes in this way */ 697*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_PAGESZ_BITS 0 /* number of bits to encode the page size */ 698*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ 699*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ 700*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; 701*79bc0fb5SMax Filippov 2^PAGESZ_BITS entries in list, unsupported entries are zero */ 702*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ 703*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ 704*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ 705*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ 706*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ 707*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ 708*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ 709*79bc0fb5SMax Filippov #define XCHAL_DTLB_SET9_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ 710*79bc0fb5SMax Filippov 711*79bc0fb5SMax Filippov 712*79bc0fb5SMax Filippov 713*79bc0fb5SMax Filippov 714*79bc0fb5SMax Filippov #endif /* XTENSA_CONFIG_CORE_MATMAP_H */ 715*79bc0fb5SMax Filippov 716