1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
31 #define SPRGROUP_IC	(4 << MAX_SPRS_PER_GRP_BITS)
45 #define SPR_IMMUCFGR	(SPRGROUP_SYS + 4)
72 #define SPR_DTLBMR_BASE(WAY)	(SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)  argument
73 #define SPR_DTLBMR_LAST(WAY)	(SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)  argument
74 #define SPR_DTLBTR_BASE(WAY)	(SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)  argument
75 #define SPR_DTLBTR_LAST(WAY)	(SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)  argument
80 #define SPR_ITLBMR_BASE(WAY)	(SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)  argument
81 #define SPR_ITLBMR_LAST(WAY)	(SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)  argument
82 #define SPR_ITLBTR_BASE(WAY)	(SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)  argument
83 #define SPR_ITLBTR_LAST(WAY)	(SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)  argument
90 #define SPR_DCBWR	(SPRGROUP_DC + 4)
92 #define SPR_DCR_BASE(WAY)	(SPRGROUP_DC + 0x200 + (WAY) * 0x200)  argument
93 #define SPR_DCR_LAST(WAY)	(SPRGROUP_DC + 0x3ff + (WAY) * 0x200)  argument
100 #define SPR_ICR_BASE(WAY)	(SPRGROUP_IC + 0x200 + (WAY) * 0x200)  argument
101 #define SPR_ICR_LAST(WAY)	(SPRGROUP_IC + 0x3ff + (WAY) * 0x200)  argument
204                                4 == n ? SPR_DCFGR_NDP4 : \
269 #define SPR_DTLBTR_WBC	   0x00000004  /* Write-Back Cache */
270 #define SPR_DTLBTR_WOM	   0x00000008  /* Weakly-Ordered Memory */
295 #define SPR_ITLBTR_WBC	   0x00000004  /* Write-Back Cache */
296 #define SPR_ITLBTR_WOM	   0x00000008  /* Weakly-Ordered Memory */
410 /* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
448 #define SPR_DMR1_ST	  0x00400000  /* Single-step trace*/