arm/mm/cache-v7.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/mm/cache-v7.S
15 #include <asm/hardware/cache-b15-rac.h>
17 #include "proc-macros.S"
19 .arch armv7-a
51 	mov	r3, r3, lsl r1		@ NumWays-1 shifted into bits [31:...]
53 	moveq	r1, #1			@ r1 needs value > 0 even if only 1 way
56 	add	r2, r2, #4		@ SetShift
64 	subs	r0, r0, #1		@ Set--
66 	subs	r3, r3, r1		@ Way--
68 	mrc	p15, 1, r0, c0, c0, 0	@ re-read cache geometry from CCSIDR
78  *	Flush the whole I-cache.
81  *	r0 - set to 0
85 	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
93  *     Flush the D-cache up to the Level of Unification Inner Shareable
95  *     Corrupted registers: r0-r6, r9-r10
108 	movw	r1, #:lower16:(0x410fc090 >> 4)	@ ID of ARM Cortex A9 r0p?
109 	movt	r1, #:upper16:(0x410fc090 >> 4)
110 	teq	r1, r2, lsr #4			@ test for errata affected core and if so...
120  *	Flush the whole D-cache.
122  *	Corrupted registers: r0-r6, r9-r10
124  *	- mm    - mm_struct describing address space
139 	blt	skip				@ skip if no cache, or just i-cache
150 	add	r2, r2, #4			@ add 4 (line length offset)
152 	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
153 	clz	r5, r4				@ find bit position of way size increment
163 	orr	r5, r5, r4			@ factor way number into r5
165 	mcr	p15, 0, r5, c7, c14, 2		@ clean & invalidate by set/way
168 	subs	r4, r4, r6			@ decrement the way
190  *  working outwards from L1 cache. This is done using Set/Way based cache
197 	stmfd	sp!, {r4-r6, r9-r10, lr}
200 	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)	@ invalidate I-cache inner shareable
202 	ldmfd	sp!, {r4-r6, r9-r10, lr}
210  *     Invalidate the I-cache to the point of unification.
213 	stmfd	sp!, {r4-r6, r9-r10, lr}
216 	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)	@ invalidate I-cache inner shareable
218 	ldmfd	sp!, {r4-r6, r9-r10, lr}
227  *	- mm    - mm_struct describing address space
237  *	- start - start address (may not be aligned)
238  *	- end   - end address (exclusive, may not be aligned)
239  *	- flags	- vm_area_struct flags describing address space
242  *	- we have a VIPT cache.
256  *	- start   - virtual start address of region
257  *	- end     - virtual end address of region
260  *	- the Icache does not read data from the write buffer
272  *	- start   - virtual start address of region
273  *	- end     - virtual end address of region
276  *	- the Icache does not read data from the write buffer
315  * isn't mapped, fail with -EFAULT.
321 	mov	r0, #-EFAULT
333  *	- addr	- kernel address
334  *	- size	- region size
361  *	- start   - virtual start address of region
362  *	- end     - virtual end address of region
391  *	- start   - virtual start address of region
392  *	- end     - virtual end address of region
413  *	- start   - virtual start address of region
414  *	- end     - virtual end address of region
435  *	- start	- kernel virtual start address
436  *	- size	- size of region
437  *	- dir	- DMA direction
448  *	- start	- kernel virtual start address
449  *	- size	- size of region
450  *	- dir	- DMA direction
461 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
464 	/* The Broadcom Brahma-B15 read-ahead cache requires some modifications