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/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c18 * <http://www.gnu.org/licenses/gpl-2.0.html>
23 #include "cpu.h"
26 #include "hw/qdev-properties.h"
29 #include "cpu-features.h"
34 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
36 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
37 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
38 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
39 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
40 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a35_initfn()
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/openbmc/qemu/docs/system/s390x/
H A Dcpu-topology.rst1 .. _cpu-topology-s390x:
3 CPU topology on s390x
6 Since QEMU 8.2, CPU topology on s390x provides up to 3 levels of
8 tree-shaped hierarchy.
10 The socket container has one or more CPU entries.
11 Each of these CPU entries consists of a bitmap and three CPU attributes:
13 - CPU type
14 - entitlement
15 - dedication
17 Each bit set in the bitmap correspond to a core-id of a vCPU with matching
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/openbmc/qemu/hw/intc/
H A Dloongarch_extioi.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 #include "hw/qdev-properties.h"
16 #include "exec/address-spaces.h"
24 int ipnum, cpu, found, irq_index, irq_mask; in extioi_update_irq() local
26 ipnum = s->sw_ipmap[irq / 32]; in extioi_update_irq()
27 cpu = s->sw_coremap[irq]; in extioi_update_irq()
33 if (((s->enable[irq_index]) & irq_mask) == 0) { in extioi_update_irq()
36 s->cpu[cpu].coreisr[irq_index] |= irq_mask; in extioi_update_irq()
37 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS); in extioi_update_irq()
38 set_bit(irq, s->cpu[cpu].sw_isr[ipnum]); in extioi_update_irq()
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/openbmc/qemu/docs/system/
H A Dcpu-models-mips.rst.inc1 Supported CPU model configurations on MIPS hosts
4 QEMU supports variety of MIPS CPU models:
6 Supported CPU models for MIPS32 hosts
9 The following CPU models are supported for use on MIPS32 hosts.
10 Administrators / applications are recommended to use the CPU model that
12 mixture of host CPU models between machines, if live migration
13 compatibility is required, use the newest CPU model that is compatible
16 ``mips32r6-generic``
34 ``4Kc``, ``4Km``, ``4KEcR1``, ``4KEmR1``, ``4KEc``, ``4KEm``
35 MIPS32 Processor (4K, 1999)
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/openbmc/linux/Documentation/translations/zh_CN/core-api/
H A Dcpu_hotplug.rst1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/core-api/cpu_hotplug.rst
85 hot-add/hot-remove。目前还没有定死规定。典型的用法是在启动时启动拓扑结构，这时
101 $ ls -lh /sys/devices/system/cpu
103 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu0
104 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu1
105 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu2
106 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu3
107 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu4
108 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu5
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/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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/openbmc/qemu/target/arm/hvf/
H A Dhvf.c8 * See the COPYING file in the top-level directory.
13 #include "qemu/error-report.h"
24 #include "exec/address-spaces.h"
27 #include "qemu/main-loop.h"
29 #include "arm-powerctl.h"
30 #include "target/arm/cpu.h"
183 #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4)
184 #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4)
185 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
193 #define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4)
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/openbmc/linux/Documentation/core-api/
H A Dcpu_hotplug.rst2 CPU hotplug in the Kernel
19 insertion and removal require support for CPU hotplug.
22 provisioning reasons, or for RAS purposes to keep an offending CPU off
23 system execution path. Hence the need for CPU hotplug support in the
26 A more novel use of CPU-hotplug support is its use today in suspend resume
27 support for SMP. Dual-core and HT support makes even a laptop run SMP kernels
59 CPU maps
72 after a CPU is available for kernel scheduling and ready to receive
73 interrupts from devices. Its cleared when a CPU is brought down using
75 migrated to another target CPU.
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/openbmc/linux/arch/arm64/boot/dts/cavium/
H A Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
63 #size-cells = <0>;
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/openbmc/linux/arch/arm64/kernel/
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
27 * may prevent a CPU from being onlined at all.
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
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/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 cpu@900 {
22 compatible = "arm,cortex-a9";
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H A Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
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/openbmc/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
8 collection of features that give more granular control over CPU performance.
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
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/openbmc/linux/include/linux/irqchip/
H A Dirq-bcm2836.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
13 * next 2 bits identify the CPU that the GPU FIQ goes to.
16 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
18 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
21 * The low 4 bits of this are the CPU's timer IRQ enables, and the
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
27 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
33 * The CPU's interrupt status register. Bits are defined by the
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/openbmc/qemu/target/ppc/
H A Dmachine.c2 #include "cpu.h"
3 #include "exec/exec-all.h"
7 #include "mmu-hash64.h"
8 #include "migration/cpu.h"
11 #include "power8-pmu.h"
16 target_ulong msr = env->msr; in post_load_update_msr()
22 env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); in post_load_update_msr()
31 v->u64[0] = qemu_get_be64(f); in get_avr()
32 v->u64[1] = qemu_get_be64(f); in get_avr()
42 qemu_put_be64(f, v->u64[0]); in put_avr()
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/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
10 #include <asm/arch/imx-regs.h>
104 #define imx_cpu_gpr_entry_offset(cpu) \ argument
105 (SRC_BASE_ADDR + SRC_GPR1_MX7D + cpu * 8)
106 #define imx_cpu_gpr_para_offset(cpu) \ argument
107 (imx_cpu_gpr_entry_offset(cpu) + 4)
137 static inline void psci_set_state(int cpu, u8 state) in psci_set_state() argument
139 psci_state[cpu] = state; in psci_set_state()
149 __secure void imx_gpcv2_set_core_power(int cpu, bool pdn) in imx_gpcv2_set_core_power() argument
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/openbmc/linux/Documentation/admin-guide/
H A Dcputopology.rst2 How CPU topology info is exported via sysfs
5 CPU topology info is exported via sysfs. Items (attributes) are similar
7 /sys/devices/system/cpu/cpuX/topology/. Please refer to the ABI file:
8 Documentation/ABI/stable/sysfs-devices-system-cpu.
10 Architecture-neutral, drivers/base/topology.c, exports these attributes.
16 these macros in include/asm-XXX/topology.h::
18 #define topology_physical_package_id(cpu)
19 #define topology_die_id(cpu)
20 #define topology_cluster_id(cpu)
21 #define topology_core_id(cpu)
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/openbmc/linux/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
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/openbmc/qemu/target/i386/
H A Dhost-cpu.c2 * x86 host CPU functions, and "host" cpu type initialization
7 * See the COPYING file in the top-level directory.
11 #include "cpu.h"
12 #include "host-cpu.h"
14 #include "qemu/error-report.h"
17 /* Note: Only safe for use on x86(-64) hosts */
45 static void host_cpu_adjust_phys_bits(X86CPU *cpu) in host_cpu_adjust_phys_bits() argument
48 uint32_t phys_bits = cpu->phys_bits; in host_cpu_adjust_phys_bits()
56 " does not match phys-bits property (%u)", in host_cpu_adjust_phys_bits()
60 if (cpu->host_phys_bits) { in host_cpu_adjust_phys_bits()
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H A Dgdbstub.c4 * Copyright (c) 2003-2005 Fabrice Bellard
21 #include "accel/tcg/vcpu-state.h"
22 #include "cpu.h"
26 #include "linux-user/qemu.h"
37 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
41 * gdb_num_core_regs in target/i386/cpu.c
50 * general regs -----> 8 or 16
58 * fpu regs ----------> 8 or 16
62 * total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
77 #define IDX_CTL_CR8_REG (IDX_CTL_REGS + 4)
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/openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Duncore-io.json148 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
154 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
203 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
209 …plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
300 "BriefDescription": "PCIe Completion Buffer Occupancy : Part 4",
344 "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0-7",
354 "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
360 …"PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of …
365 "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
371 …"PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of …
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/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dsubcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/cpu.h>
32 * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
37 * ------------|------------------
39 * 2-way split | 2
40 * 4-way split | 4
46 * ----------------------------
48 * ----------------------------
49 * Thread | 0 1 2 3 4 5 6 7 |
50 * ----------------------------
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/openbmc/linux/tools/perf/tests/
H A Dcpumap.c1 // SPDX-License-Identifier: GPL-2.0
6 #include "util/synthetic-events.h"
19 struct perf_record_cpu_map *map_event = &event->cpu_map; in process_event_mask()
24 data = &map_event->data; in process_event_mask()
26 TEST_ASSERT_VAL("wrong type", data->type == PERF_CPU_MAP__MASK); in process_event_mask()
28 long_size = data->mask32_data.long_size; in process_event_mask()
30 TEST_ASSERT_VAL("wrong long_size", long_size == 4 || long_size == 8); in process_event_mask()
32 TEST_ASSERT_VAL("wrong nr", data->mask32_data.nr == 1); in process_event_mask()
34 TEST_ASSERT_VAL("wrong cpu", perf_record_cpu_map_data__test_bit(0, data)); in process_event_mask()
35 TEST_ASSERT_VAL("wrong cpu", !perf_record_cpu_map_data__test_bit(1, data)); in process_event_mask()
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