1c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 288bbe85dSStefan Wahren /* 388bbe85dSStefan Wahren * Root interrupt controller for the BCM2836 (Raspberry Pi 2). 488bbe85dSStefan Wahren * 588bbe85dSStefan Wahren * Copyright 2015 Broadcom 688bbe85dSStefan Wahren */ 788bbe85dSStefan Wahren 888bbe85dSStefan Wahren #define LOCAL_CONTROL 0x000 988bbe85dSStefan Wahren #define LOCAL_PRESCALER 0x008 1088bbe85dSStefan Wahren 1188bbe85dSStefan Wahren /* 1288bbe85dSStefan Wahren * The low 2 bits identify the CPU that the GPU IRQ goes to, and the 1388bbe85dSStefan Wahren * next 2 bits identify the CPU that the GPU FIQ goes to. 1488bbe85dSStefan Wahren */ 1588bbe85dSStefan Wahren #define LOCAL_GPU_ROUTING 0x00c 1688bbe85dSStefan Wahren /* When setting bits 0-3, enables PMU interrupts on that CPU. */ 1788bbe85dSStefan Wahren #define LOCAL_PM_ROUTING_SET 0x010 1888bbe85dSStefan Wahren /* When setting bits 0-3, disables PMU interrupts on that CPU. */ 1988bbe85dSStefan Wahren #define LOCAL_PM_ROUTING_CLR 0x014 2088bbe85dSStefan Wahren /* 2188bbe85dSStefan Wahren * The low 4 bits of this are the CPU's timer IRQ enables, and the 2288bbe85dSStefan Wahren * next 4 bits are the CPU's timer FIQ enables (which override the IRQ 2388bbe85dSStefan Wahren * bits). 2488bbe85dSStefan Wahren */ 2588bbe85dSStefan Wahren #define LOCAL_TIMER_INT_CONTROL0 0x040 2688bbe85dSStefan Wahren /* 2788bbe85dSStefan Wahren * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and 2888bbe85dSStefan Wahren * the next 4 bits are the CPU's per-mailbox FIQ enables (which 2988bbe85dSStefan Wahren * override the IRQ bits). 3088bbe85dSStefan Wahren */ 3188bbe85dSStefan Wahren #define LOCAL_MAILBOX_INT_CONTROL0 0x050 3288bbe85dSStefan Wahren /* 33*b7640d76SRandy Dunlap * The CPU's interrupt status register. Bits are defined by the 3488bbe85dSStefan Wahren * LOCAL_IRQ_* bits below. 3588bbe85dSStefan Wahren */ 3688bbe85dSStefan Wahren #define LOCAL_IRQ_PENDING0 0x060 3788bbe85dSStefan Wahren /* Same status bits as above, but for FIQ. */ 3888bbe85dSStefan Wahren #define LOCAL_FIQ_PENDING0 0x070 3988bbe85dSStefan Wahren /* 4088bbe85dSStefan Wahren * Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and 4188bbe85dSStefan Wahren * these bits are organized by mailbox number and then CPU number. We 4288bbe85dSStefan Wahren * use mailbox 0 for IPIs. The mailbox's interrupt is raised while 4388bbe85dSStefan Wahren * any bit is set. 4488bbe85dSStefan Wahren */ 4588bbe85dSStefan Wahren #define LOCAL_MAILBOX0_SET0 0x080 4688bbe85dSStefan Wahren #define LOCAL_MAILBOX3_SET0 0x08c 4788bbe85dSStefan Wahren /* Mailbox write-to-clear bits. */ 4888bbe85dSStefan Wahren #define LOCAL_MAILBOX0_CLR0 0x0c0 4988bbe85dSStefan Wahren #define LOCAL_MAILBOX3_CLR0 0x0cc 5088bbe85dSStefan Wahren 5188bbe85dSStefan Wahren #define LOCAL_IRQ_CNTPSIRQ 0 5288bbe85dSStefan Wahren #define LOCAL_IRQ_CNTPNSIRQ 1 5388bbe85dSStefan Wahren #define LOCAL_IRQ_CNTHPIRQ 2 5488bbe85dSStefan Wahren #define LOCAL_IRQ_CNTVIRQ 3 5588bbe85dSStefan Wahren #define LOCAL_IRQ_MAILBOX0 4 5688bbe85dSStefan Wahren #define LOCAL_IRQ_MAILBOX1 5 5788bbe85dSStefan Wahren #define LOCAL_IRQ_MAILBOX2 6 5888bbe85dSStefan Wahren #define LOCAL_IRQ_MAILBOX3 7 5988bbe85dSStefan Wahren #define LOCAL_IRQ_GPU_FAST 8 6088bbe85dSStefan Wahren #define LOCAL_IRQ_PMU_FAST 9 6188bbe85dSStefan Wahren #define LAST_IRQ LOCAL_IRQ_PMU_FAST 62