Lines Matching +full:4 +full:- +full:cpu
8 * See the COPYING file in the top-level directory.
13 #include "qemu/error-report.h"
24 #include "exec/address-spaces.h"
27 #include "qemu/main-loop.h"
29 #include "arm-powerctl.h"
30 #include "target/arm/cpu.h"
183 #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4)
184 #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4)
185 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
193 #define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4)
200 #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4)
211 #define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4)
221 #define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0)
228 #define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4)
232 #define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4)
236 #define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4)
240 #define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4)
244 #define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4)
245 #define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5)
246 #define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6)
247 #define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7)
248 #define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4)
252 #define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4)
256 #define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4)
260 #define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4)
264 #define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4)
268 #define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4)
272 #define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4)
276 #define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4)
280 #define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4)
284 #define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4)
288 #define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4)
299 static void hvf_wfi(CPUState *cpu);
330 { HV_REG_X4, offsetof(CPUARMState, xregs[4]) },
365 { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) },
402 { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 4) },
407 { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 4) },
412 { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 4) },
417 { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 4) },
422 { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 4) },
423 { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 5) },
424 { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 6) },
425 { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 7) },
427 { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 4) },
432 { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 4) },
437 { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 4) },
442 { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 4) },
447 { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 4) },
452 { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 4) },
457 { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 4) },
462 { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 4) },
467 { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 4) },
472 { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 4) },
477 { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 4) },
490 { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) },
492 { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 1) },
523 { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) },
524 { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) },
525 { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) },
530 { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) },
535 { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) },
542 { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) },
545 int hvf_get_registers(CPUState *cpu) in hvf_get_registers() argument
547 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_get_registers()
548 CPUARMState *env = &arm_cpu->env; in hvf_get_registers()
555 ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val); in hvf_get_registers()
561 ret = hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, in hvf_get_registers()
568 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val); in hvf_get_registers()
573 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val); in hvf_get_registers()
577 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val); in hvf_get_registers()
582 if (hvf_sreg_match[i].cp_idx == -1) { in hvf_get_registers()
586 if (cpu->accel->guest_debug_enabled) { in hvf_get_registers()
663 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key); in hvf_get_registers()
666 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; in hvf_get_registers()
672 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val); in hvf_get_registers()
675 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; in hvf_get_registers()
684 int hvf_put_registers(CPUState *cpu) in hvf_put_registers() argument
686 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_put_registers()
687 CPUARMState *env = &arm_cpu->env; in hvf_put_registers()
695 ret = hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); in hvf_put_registers()
701 ret = hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, in hvf_put_registers()
706 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env)); in hvf_put_registers()
709 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env)); in hvf_put_registers()
712 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env)); in hvf_put_registers()
719 if (hvf_sreg_match[i].cp_idx == -1) { in hvf_put_registers()
723 if (cpu->accel->guest_debug_enabled) { in hvf_put_registers()
799 val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; in hvf_put_registers()
800 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, val); in hvf_put_registers()
804 ret = hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_offset); in hvf_put_registers()
810 static void flush_cpu_state(CPUState *cpu) in flush_cpu_state() argument
812 if (cpu->accel->dirty) { in flush_cpu_state()
813 hvf_put_registers(cpu); in flush_cpu_state()
814 cpu->accel->dirty = false; in flush_cpu_state()
818 static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) in hvf_set_reg() argument
822 flush_cpu_state(cpu); in hvf_set_reg()
825 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val); in hvf_set_reg()
830 static uint64_t hvf_get_reg(CPUState *cpu, int rt) in hvf_get_reg() argument
835 flush_cpu_state(cpu); in hvf_get_reg()
838 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val); in hvf_get_reg()
879 ahcf->dtb_compatible = "arm,arm-v8"; in hvf_arm_get_host_cpu_features()
880 ahcf->features = (1ULL << ARM_FEATURE_V8) | in hvf_arm_get_host_cpu_features()
895 r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); in hvf_arm_get_host_cpu_features()
900 ahcf->isar = host_isar; in hvf_arm_get_host_cpu_features()
906 ahcf->reset_sctlr = 0x30100180; in hvf_arm_get_host_cpu_features()
912 ahcf->reset_sctlr |= 0x00800000; in hvf_arm_get_host_cpu_features()
946 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) in hvf_arm_set_cpu_features_from_host() argument
955 cpu->host_cpu_probe_failed = true; in hvf_arm_set_cpu_features_from_host()
960 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; in hvf_arm_set_cpu_features_from_host()
961 cpu->isar = arm_host_cpu_features.isar; in hvf_arm_set_cpu_features_from_host()
962 cpu->env.features = arm_host_cpu_features.features; in hvf_arm_set_cpu_features_from_host()
963 cpu->midr = arm_host_cpu_features.midr; in hvf_arm_set_cpu_features_from_host()
964 cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; in hvf_arm_set_cpu_features_from_host()
967 void hvf_arch_vcpu_destroy(CPUState *cpu) in hvf_arch_vcpu_destroy() argument
990 int hvf_arch_init_vcpu(CPUState *cpu) in hvf_arch_init_vcpu() argument
992 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_arch_init_vcpu()
993 CPUARMState *env = &arm_cpu->env; in hvf_arch_init_vcpu()
1000 env->aarch64 = true; in hvf_arch_init_vcpu()
1001 asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); in hvf_arch_init_vcpu()
1004 arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, in hvf_arch_init_vcpu()
1006 arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, in hvf_arch_init_vcpu()
1008 arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, in hvf_arch_init_vcpu()
1009 arm_cpu->cpreg_vmstate_indexes, in hvf_arch_init_vcpu()
1011 arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, in hvf_arch_init_vcpu()
1012 arm_cpu->cpreg_vmstate_values, in hvf_arch_init_vcpu()
1015 memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); in hvf_arch_init_vcpu()
1022 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); in hvf_arch_init_vcpu()
1024 assert(!(ri->type & ARM_CP_NO_RAW)); in hvf_arch_init_vcpu()
1026 arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); in hvf_arch_init_vcpu()
1028 hvf_sreg_match[i].cp_idx = -1; in hvf_arch_init_vcpu()
1031 arm_cpu->cpreg_array_len = sregs_cnt; in hvf_arch_init_vcpu()
1032 arm_cpu->cpreg_vmstate_array_len = sregs_cnt; in hvf_arch_init_vcpu()
1037 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1, in hvf_arch_init_vcpu()
1038 arm_cpu->midr); in hvf_arch_init_vcpu()
1041 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, in hvf_arch_init_vcpu()
1042 arm_cpu->mp_affinity); in hvf_arch_init_vcpu()
1045 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); in hvf_arch_init_vcpu()
1047 pfr |= env->gicv3state ? (1 << 24) : 0; in hvf_arch_init_vcpu()
1048 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); in hvf_arch_init_vcpu()
1052 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, in hvf_arch_init_vcpu()
1053 &arm_cpu->isar.id_aa64mmfr0); in hvf_arch_init_vcpu()
1056 clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar.id_aa64mmfr0); in hvf_arch_init_vcpu()
1057 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, in hvf_arch_init_vcpu()
1058 arm_cpu->isar.id_aa64mmfr0); in hvf_arch_init_vcpu()
1064 void hvf_kick_vcpu_thread(CPUState *cpu) in hvf_kick_vcpu_thread() argument
1066 cpus_kick_thread(cpu); in hvf_kick_vcpu_thread()
1067 hv_vcpus_exit(&cpu->accel->fd, 1); in hvf_kick_vcpu_thread()
1070 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, in hvf_raise_exception() argument
1073 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_raise_exception()
1074 CPUARMState *env = &arm_cpu->env; in hvf_raise_exception()
1076 cpu->exception_index = excp; in hvf_raise_exception()
1077 env->exception.target_el = 1; in hvf_raise_exception()
1078 env->exception.syndrome = syndrome; in hvf_raise_exception()
1080 arm_cpu_do_interrupt(cpu); in hvf_raise_exception()
1093 * -1 when the PSCI call is unknown,
1095 static bool hvf_handle_psci_call(CPUState *cpu) in hvf_handle_psci_call() argument
1097 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_handle_psci_call()
1098 CPUARMState *env = &arm_cpu->env; in hvf_handle_psci_call()
1099 uint64_t param[4] = { in hvf_handle_psci_call()
1100 env->xregs[0], in hvf_handle_psci_call()
1101 env->xregs[1], in hvf_handle_psci_call()
1102 env->xregs[2], in hvf_handle_psci_call()
1103 env->xregs[3] in hvf_handle_psci_call()
1136 ret = target_cpu->power_state; in hvf_handle_psci_call()
1148 * call, so power the CPU off now so it doesn't execute in hvf_handle_psci_call()
1179 env->xregs[0] = 0; in hvf_handle_psci_call()
1180 hvf_wfi(cpu); in hvf_handle_psci_call()
1215 env->xregs[0] = ret; in hvf_handle_psci_call()
1238 static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) in hvf_sysreg_read_cp() argument
1240 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_sysreg_read_cp()
1241 CPUARMState *env = &arm_cpu->env; in hvf_sysreg_read_cp()
1244 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); in hvf_sysreg_read_cp()
1246 if (ri->accessfn) { in hvf_sysreg_read_cp()
1247 if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) { in hvf_sysreg_read_cp()
1251 if (ri->type & ARM_CP_CONST) { in hvf_sysreg_read_cp()
1252 *val = ri->resetvalue; in hvf_sysreg_read_cp()
1253 } else if (ri->readfn) { in hvf_sysreg_read_cp()
1254 *val = ri->readfn(env, ri); in hvf_sysreg_read_cp()
1258 trace_hvf_vgic_read(ri->name, *val); in hvf_sysreg_read_cp()
1265 static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val) in hvf_sysreg_read() argument
1267 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_sysreg_read()
1268 CPUARMState *env = &arm_cpu->env; in hvf_sysreg_read()
1273 *val = env->cp15.c9_pmcr; in hvf_sysreg_read()
1277 *val = env->cp15.c15_ccnt; in hvf_sysreg_read()
1281 *val = env->cp15.c9_pmcnten; in hvf_sysreg_read()
1284 *val = env->cp15.c9_pmovsr; in hvf_sysreg_read()
1287 *val = env->cp15.c9_pmselr; in hvf_sysreg_read()
1290 *val = env->cp15.c9_pminten; in hvf_sysreg_read()
1293 *val = env->cp15.pmccfiltr_el0; in hvf_sysreg_read()
1296 *val = env->cp15.c9_pmcnten; in hvf_sysreg_read()
1299 *val = env->cp15.c9_pmuserenr; in hvf_sysreg_read()
1315 *val = env->cp15.oslsr_el1; in hvf_sysreg_read()
1346 if (hvf_sysreg_read_cp(cpu, reg, val)) { in hvf_sysreg_read()
1366 *val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; in hvf_sysreg_read()
1384 *val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; in hvf_sysreg_read()
1402 *val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; in hvf_sysreg_read()
1420 *val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; in hvf_sysreg_read()
1430 cpu_synchronize_state(cpu); in hvf_sysreg_read()
1431 trace_hvf_unhandled_sysreg_read(env->pc, reg, in hvf_sysreg_read()
1437 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); in hvf_sysreg_read()
1443 ARMCPU *cpu = env_archcpu(env); in pmu_update_irq() local
1444 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && in pmu_update_irq()
1445 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); in pmu_update_irq()
1462 enabled = (env->cp15.c9_pmcr & PMCRE) && in pmu_counter_enabled()
1463 (env->cp15.c9_pmcnten & (1 << counter)); in pmu_counter_enabled()
1466 filter = env->cp15.pmccfiltr_el0; in pmu_counter_enabled()
1468 filter = env->cp15.c14_pmevtyper[counter]; in pmu_counter_enabled()
1500 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { in pmswinc_write()
1505 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; in pmswinc_write()
1507 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { in pmswinc_write()
1508 env->cp15.c9_pmovsr |= (1 << i); in pmswinc_write()
1512 env->cp15.c14_pmevcntr[i] = new_pmswinc; in pmswinc_write()
1517 static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) in hvf_sysreg_write_cp() argument
1519 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_sysreg_write_cp()
1520 CPUARMState *env = &arm_cpu->env; in hvf_sysreg_write_cp()
1523 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); in hvf_sysreg_write_cp()
1526 if (ri->accessfn) { in hvf_sysreg_write_cp()
1527 if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) { in hvf_sysreg_write_cp()
1531 if (ri->writefn) { in hvf_sysreg_write_cp()
1532 ri->writefn(env, ri, val); in hvf_sysreg_write_cp()
1537 trace_hvf_vgic_write(ri->name, val); in hvf_sysreg_write_cp()
1544 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) in hvf_sysreg_write() argument
1546 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_sysreg_write()
1547 CPUARMState *env = &arm_cpu->env; in hvf_sysreg_write()
1561 env->cp15.c15_ccnt = val; in hvf_sysreg_write()
1569 env->cp15.c15_ccnt = 0; in hvf_sysreg_write()
1575 env->cp15.c14_pmevcntr[i] = 0; in hvf_sysreg_write()
1579 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; in hvf_sysreg_write()
1580 env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); in hvf_sysreg_write()
1585 env->cp15.c9_pmuserenr = val & 0xf; in hvf_sysreg_write()
1588 env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); in hvf_sysreg_write()
1591 env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); in hvf_sysreg_write()
1595 env->cp15.c9_pminten |= val; in hvf_sysreg_write()
1600 env->cp15.c9_pmovsr &= ~val; in hvf_sysreg_write()
1609 env->cp15.c9_pmselr = val & 0x1f; in hvf_sysreg_write()
1613 env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; in hvf_sysreg_write()
1621 env->cp15.oslsr_el1 = val & 1; in hvf_sysreg_write()
1652 if (hvf_sysreg_write_cp(cpu, reg, val)) { in hvf_sysreg_write()
1657 env->cp15.mdscr_el1 = val; in hvf_sysreg_write()
1675 env->cp15.dbgbvr[SYSREG_CRM(reg)] = val; in hvf_sysreg_write()
1693 env->cp15.dbgbcr[SYSREG_CRM(reg)] = val; in hvf_sysreg_write()
1711 env->cp15.dbgwvr[SYSREG_CRM(reg)] = val; in hvf_sysreg_write()
1729 env->cp15.dbgwcr[SYSREG_CRM(reg)] = val; in hvf_sysreg_write()
1733 cpu_synchronize_state(cpu); in hvf_sysreg_write()
1734 trace_hvf_unhandled_sysreg_write(env->pc, reg, in hvf_sysreg_write()
1740 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); in hvf_sysreg_write()
1744 static int hvf_inject_interrupts(CPUState *cpu) in hvf_inject_interrupts() argument
1746 if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { in hvf_inject_interrupts()
1748 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FIQ, in hvf_inject_interrupts()
1752 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { in hvf_inject_interrupts()
1754 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IRQ, in hvf_inject_interrupts()
1767 return mach_absolute_time() - hvf_state->vtimer_offset; in hvf_vtimer_val_raw()
1780 static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) in hvf_wait_for_ipi() argument
1786 qatomic_set_mb(&cpu->thread_kicked, false); in hvf_wait_for_ipi()
1788 pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask); in hvf_wait_for_ipi()
1792 static void hvf_wfi(CPUState *cpu) in hvf_wfi() argument
1794 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_wfi()
1804 if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { in hvf_wfi()
1809 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); in hvf_wfi()
1814 hvf_wait_for_ipi(cpu, NULL); in hvf_wfi()
1818 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval); in hvf_wfi()
1821 ticks_to_sleep = cval - hvf_vtimer_val(); in hvf_wfi()
1828 ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq); in hvf_wfi()
1833 * so that we can satisfy fast timer requests on the same CPU. in hvf_wfi()
1841 hvf_wait_for_ipi(cpu, &ts); in hvf_wfi()
1844 static void hvf_sync_vtimer(CPUState *cpu) in hvf_sync_vtimer() argument
1846 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_sync_vtimer()
1851 if (!cpu->accel->vtimer_masked) { in hvf_sync_vtimer()
1856 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); in hvf_sync_vtimer()
1861 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); in hvf_sync_vtimer()
1865 hv_vcpu_set_vtimer_mask(cpu->accel->fd, false); in hvf_sync_vtimer()
1866 cpu->accel->vtimer_masked = false; in hvf_sync_vtimer()
1870 int hvf_vcpu_exec(CPUState *cpu) in hvf_vcpu_exec() argument
1872 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_vcpu_exec()
1873 CPUARMState *env = &arm_cpu->env; in hvf_vcpu_exec()
1875 hv_vcpu_exit_t *hvf_exit = cpu->accel->exit; in hvf_vcpu_exec()
1879 if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) && in hvf_vcpu_exec()
1880 hvf_inject_interrupts(cpu)) { in hvf_vcpu_exec()
1884 if (cpu->halted) { in hvf_vcpu_exec()
1888 flush_cpu_state(cpu); in hvf_vcpu_exec()
1891 assert_hvf_ok(hv_vcpu_run(cpu->accel->fd)); in hvf_vcpu_exec()
1894 uint64_t exit_reason = hvf_exit->reason; in hvf_vcpu_exec()
1895 uint64_t syndrome = hvf_exit->exception.syndrome; in hvf_vcpu_exec()
1905 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); in hvf_vcpu_exec()
1906 cpu->accel->vtimer_masked = true; in hvf_vcpu_exec()
1915 hvf_sync_vtimer(cpu); in hvf_vcpu_exec()
1921 if (!cpu->singlestep_enabled) { in hvf_vcpu_exec()
1922 error_report("EC_SOFTWARESTEP but single-stepping not enabled"); in hvf_vcpu_exec()
1929 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
1931 if (!hvf_find_sw_breakpoint(cpu, env->pc)) { in hvf_vcpu_exec()
1932 /* Re-inject into the guest */ in hvf_vcpu_exec()
1934 hvf_raise_exception(cpu, EXCP_BKPT, syn_aa64_bkpt(0)); in hvf_vcpu_exec()
1941 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
1943 if (!find_hw_breakpoint(cpu, env->pc)) { in hvf_vcpu_exec()
1951 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
1954 find_hw_watchpoint(cpu, hvf_exit->exception.virtual_address); in hvf_vcpu_exec()
1958 cpu->watchpoint_hit = wp; in hvf_vcpu_exec()
1971 trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address, in hvf_vcpu_exec()
1972 hvf_exit->exception.physical_address, isv, in hvf_vcpu_exec()
1984 val = hvf_get_reg(cpu, srt); in hvf_vcpu_exec()
1986 hvf_exit->exception.physical_address, in hvf_vcpu_exec()
1990 hvf_exit->exception.physical_address, in hvf_vcpu_exec()
1992 hvf_set_reg(cpu, srt, val); in hvf_vcpu_exec()
2006 sysreg_ret = hvf_sysreg_read(cpu, reg, &val); in hvf_vcpu_exec()
2015 hvf_set_reg(cpu, rt, val); in hvf_vcpu_exec()
2018 val = hvf_get_reg(cpu, rt); in hvf_vcpu_exec()
2019 sysreg_ret = hvf_sysreg_write(cpu, reg, val); in hvf_vcpu_exec()
2028 hvf_wfi(cpu); in hvf_vcpu_exec()
2032 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
2033 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) { in hvf_vcpu_exec()
2034 if (!hvf_handle_psci_call(cpu)) { in hvf_vcpu_exec()
2035 trace_hvf_unknown_hvc(env->xregs[0]); in hvf_vcpu_exec()
2036 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ in hvf_vcpu_exec()
2037 env->xregs[0] = -1; in hvf_vcpu_exec()
2040 trace_hvf_unknown_hvc(env->xregs[0]); in hvf_vcpu_exec()
2041 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); in hvf_vcpu_exec()
2045 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
2046 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { in hvf_vcpu_exec()
2049 if (!hvf_handle_psci_call(cpu)) { in hvf_vcpu_exec()
2050 trace_hvf_unknown_smc(env->xregs[0]); in hvf_vcpu_exec()
2051 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ in hvf_vcpu_exec()
2052 env->xregs[0] = -1; in hvf_vcpu_exec()
2055 trace_hvf_unknown_smc(env->xregs[0]); in hvf_vcpu_exec()
2056 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); in hvf_vcpu_exec()
2060 cpu_synchronize_state(cpu); in hvf_vcpu_exec()
2061 trace_hvf_exit(syndrome, ec, env->pc); in hvf_vcpu_exec()
2062 error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); in hvf_vcpu_exec()
2068 flush_cpu_state(cpu); in hvf_vcpu_exec()
2070 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc); in hvf_vcpu_exec()
2072 pc += 4; in hvf_vcpu_exec()
2073 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc); in hvf_vcpu_exec()
2076 /* Handle single-stepping over instructions which trigger a VM exit */ in hvf_vcpu_exec()
2077 if (cpu->singlestep_enabled) { in hvf_vcpu_exec()
2086 .name = "hvf-vtimer",
2101 hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val; in hvf_vm_state_change()
2105 s->vtimer_val = hvf_vtimer_val_raw(); in hvf_vm_state_change()
2111 hvf_state->vtimer_offset = mach_absolute_time(); in hvf_arch_init()
2122 int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) in hvf_arch_insert_sw_breakpoint() argument
2124 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || in hvf_arch_insert_sw_breakpoint()
2125 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { in hvf_arch_insert_sw_breakpoint()
2126 return -EINVAL; in hvf_arch_insert_sw_breakpoint()
2131 int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) in hvf_arch_remove_sw_breakpoint() argument
2135 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk, 4, 0) || in hvf_arch_remove_sw_breakpoint()
2137 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { in hvf_arch_remove_sw_breakpoint()
2138 return -EINVAL; in hvf_arch_remove_sw_breakpoint()
2153 return -ENOSYS; in hvf_arch_insert_hw_breakpoint()
2167 return -ENOSYS; in hvf_arch_remove_hw_breakpoint()
2186 static void hvf_put_gdbstub_debug_registers(CPUState *cpu) in hvf_put_gdbstub_debug_registers() argument
2193 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr); in hvf_put_gdbstub_debug_registers()
2195 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], bp->bvr); in hvf_put_gdbstub_debug_registers()
2199 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 0); in hvf_put_gdbstub_debug_registers()
2201 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 0); in hvf_put_gdbstub_debug_registers()
2207 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr); in hvf_put_gdbstub_debug_registers()
2209 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr); in hvf_put_gdbstub_debug_registers()
2213 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 0); in hvf_put_gdbstub_debug_registers()
2215 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 0); in hvf_put_gdbstub_debug_registers()
2224 static void hvf_put_guest_debug_registers(CPUState *cpu) in hvf_put_guest_debug_registers() argument
2226 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_put_guest_debug_registers()
2227 CPUARMState *env = &arm_cpu->env; in hvf_put_guest_debug_registers()
2232 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], in hvf_put_guest_debug_registers()
2233 env->cp15.dbgbcr[i]); in hvf_put_guest_debug_registers()
2235 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], in hvf_put_guest_debug_registers()
2236 env->cp15.dbgbvr[i]); in hvf_put_guest_debug_registers()
2241 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], in hvf_put_guest_debug_registers()
2242 env->cp15.dbgwcr[i]); in hvf_put_guest_debug_registers()
2244 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], in hvf_put_guest_debug_registers()
2245 env->cp15.dbgwvr[i]); in hvf_put_guest_debug_registers()
2250 static inline bool hvf_arm_hw_debug_active(CPUState *cpu) in hvf_arm_hw_debug_active() argument
2257 CPUState *cpu; in hvf_arch_set_traps() local
2263 CPU_FOREACH(cpu) { in hvf_arch_set_traps()
2264 should_enable_traps |= cpu->accel->guest_debug_enabled; in hvf_arch_set_traps()
2266 CPU_FOREACH(cpu) { in hvf_arch_set_traps()
2268 r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd, in hvf_arch_set_traps()
2273 r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd, in hvf_arch_set_traps()
2279 void hvf_arch_update_guest_debug(CPUState *cpu) in hvf_arch_update_guest_debug() argument
2281 ARMCPU *arm_cpu = ARM_CPU(cpu); in hvf_arch_update_guest_debug()
2282 CPUARMState *env = &arm_cpu->env; in hvf_arch_update_guest_debug()
2285 cpu->accel->guest_debug_enabled = cpu->singlestep_enabled || in hvf_arch_update_guest_debug()
2286 hvf_sw_breakpoints_active(cpu) || in hvf_arch_update_guest_debug()
2287 hvf_arm_hw_debug_active(cpu); in hvf_arch_update_guest_debug()
2290 if (cpu->accel->guest_debug_enabled) { in hvf_arch_update_guest_debug()
2291 hvf_put_gdbstub_debug_registers(cpu); in hvf_arch_update_guest_debug()
2293 hvf_put_guest_debug_registers(cpu); in hvf_arch_update_guest_debug()
2296 cpu_synchronize_state(cpu); in hvf_arch_update_guest_debug()
2298 /* Enable/disable single-stepping */ in hvf_arch_update_guest_debug()
2299 if (cpu->singlestep_enabled) { in hvf_arch_update_guest_debug()
2300 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug()
2301 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1); in hvf_arch_update_guest_debug()
2304 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug()
2305 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0); in hvf_arch_update_guest_debug()
2309 if (hvf_arm_hw_debug_active(cpu)) { in hvf_arch_update_guest_debug()
2310 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug()
2311 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1); in hvf_arch_update_guest_debug()
2313 env->cp15.mdscr_el1 = in hvf_arch_update_guest_debug()
2314 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0); in hvf_arch_update_guest_debug()