1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
10 #include <asm/arch/imx-regs.h>
104 #define imx_cpu_gpr_entry_offset(cpu) \  argument
105 	(SRC_BASE_ADDR + SRC_GPR1_MX7D + cpu * 8)
106 #define imx_cpu_gpr_para_offset(cpu) \  argument
107 	(imx_cpu_gpr_entry_offset(cpu) + 4)
137 static inline void psci_set_state(int cpu, u8 state)  in psci_set_state()  argument
139 	psci_state[cpu] = state;  in psci_set_state()
149 __secure void imx_gpcv2_set_core_power(int cpu, bool pdn)  in imx_gpcv2_set_core_power()  argument
152 	u32 pgc = cpu ? GPC_PGC_C1 : GPC_PGC_C0;  in imx_gpcv2_set_core_power()
153 	u32 pdn_pup_req = cpu ? BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 :  in imx_gpcv2_set_core_power()
169 __secure void imx_enable_cpu_ca7(int cpu, bool enable)  in imx_enable_cpu_ca7()  argument
173 	mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);  in imx_enable_cpu_ca7()
181 	u32 cpu = psci_get_cpu_id();  in psci_arch_cpu_entry()  local
183 	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);  in psci_arch_cpu_entry()
189 	u32 cpu = mpidr & MPIDR_AFF0;  in psci_cpu_on()  local
194 	if (cpu >= IMX7D_PSCI_NR_CPUS)  in psci_cpu_on()
197 	if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)  in psci_cpu_on()
200 	if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING)  in psci_cpu_on()
203 	psci_save(cpu, ep, context_id);  in psci_cpu_on()
205 	writel((u32)psci_cpu_entry, imx_cpu_gpr_entry_offset(cpu));  in psci_cpu_on()
207 	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);  in psci_cpu_on()
209 	imx_gpcv2_set_core_power(cpu, true);  in psci_cpu_on()
210 	imx_enable_cpu_ca7(cpu, true);  in psci_cpu_on()
217 	int cpu;  in psci_cpu_off()  local
219 	cpu = psci_get_cpu_id();  in psci_cpu_off()
222 	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);  in psci_cpu_off()
224 	imx_enable_cpu_ca7(cpu, false);  in psci_cpu_off()
225 	imx_gpcv2_set_core_power(cpu, false);  in psci_cpu_off()
227 	 * We use the cpu jumping argument register to sync with  in psci_cpu_off()
228 	 * psci_affinity_info() which is running on cpu0 to kill the cpu.  in psci_cpu_off()
230 	writel(IMX_CPU_SYNC_OFF, imx_cpu_gpr_para_offset(cpu));  in psci_cpu_off()
243 	writew(WCR_WDE, &wdog->wcr);  in psci_system_reset()
280 	u32 cpu = target_affinity & MPIDR_AFF0;  in psci_affinity_info()  local
288 	if (cpu >= IMX7D_PSCI_NR_CPUS)  in psci_affinity_info()
291 	/* CPU is waiting for killed */  in psci_affinity_info()
292 	if (readl(imx_cpu_gpr_para_offset(cpu)) == IMX_CPU_SYNC_OFF) {  in psci_affinity_info()
293 		imx_enable_cpu_ca7(cpu, false);  in psci_affinity_info()
294 		imx_gpcv2_set_core_power(cpu, false);  in psci_affinity_info()
295 		writel(IMX_CPU_SYNC_ON, imx_cpu_gpr_para_offset(cpu));  in psci_affinity_info()
298 	return psci_state[cpu];  in psci_affinity_info()
338 	 * GPC: When improper low-power sequence is used,  in imx_gpcv2_set_lpm_mode()
345 	 *    Low-Power mode.  in imx_gpcv2_set_lpm_mode()
346 	 * 3) Software should mask IRQ #32 right after GPC Low-Power mode  in imx_gpcv2_set_lpm_mode()
391 static __secure void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu, bool pdn)  in imx_gpcv2_set_cpu_power_gate_by_lpm()  argument
396 	if (cpu == 0) {  in imx_gpcv2_set_cpu_power_gate_by_lpm()
404 	if (cpu == 1) {  in imx_gpcv2_set_cpu_power_gate_by_lpm()
424 	writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) |  in imx_gpcv2_set_slot_ack()
426 		GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4);  in imx_gpcv2_set_slot_ack()
468 	/* TYPER[4:0] contains an encoded number of available interrupts */  in gic_resume()
472 	 * from non-secure state. The first 32 interrupts are private per  in gic_resume()
473 	 * CPU and will be set later when enabling the GIC for each core  in gic_resume()
476 		writel((u32)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);  in gic_resume()
520 		if ((end - start) > usec * (freq / 1000000))  in imx_udelay()
549 	unsigned int i, val, imr[4], entry;  in imx_system_resume()
564 	for (i = 0; i < 4; i++) {  in imx_system_resume()
565 		imr[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);  in imx_system_resume()
566 		writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);  in imx_system_resume()
587 	for (i = 0; i < 4; i++)  in imx_system_resume()
588 		writel(imr[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);  in imx_system_resume()
602 	u32 gpc_mask[4];  in psci_system_suspend()
627 	 * low-power idle mode  in psci_system_suspend()
630 	 * If both CPU0/CPU1 are IDLE, the last IDLE CPU should  in psci_system_suspend()
644 	for (i = 0; i < 4; i++)  in psci_system_suspend()
645 		gpc_mask[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);  in psci_system_suspend()
665 	for (i = 0; i < 4; i++)  in psci_system_suspend()
666 		writel(gpc_mask[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);  in psci_system_suspend()