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/openbmc/qemu/tests/unit/
H A Dtest-smp-parse.c2 * SMP parsing unit-tests
10 * See the COPYING.LIB file in the top-level directory.
26 #define SMP_MACHINE_NAME "TEST-SMP"
29 * Used to define the generic 3-level CPU topology hierarchy
30 * -sockets/cores/threads
36 .has_cores = hc, .cores = c, \
45 .cores = c, \
51 * Currently a 5-level topology hierarchy is supported on PC machines
52 * -sockets/dies/modules/cores/threads
61 .has_cores = he, .cores = e, \
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/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15-tc1.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
8 * HBI-0237A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15";
18 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/openbmc/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Duncore-power.json78 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
86 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
94 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
102 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
110 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
118 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
126 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
134 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
142 …can use all four counters with this event, so it is possible to track up to 4 configurable bands. …
150 …can use all four counters with this event, so it is possible to track up to 4 configurable bands. …
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/openbmc/linux/drivers/phy/broadcom/
H A Dphy-bcm-sr-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
83 /* PIPEMUX = 2, EP 4x4 */
85 /* PIPEMUX = 3, RC 2x8, cores 0, 7 */
87 /* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
89 /* PIPEMUX = 5, RC 8x2, all 8 cores */
91 /* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
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/openbmc/u-boot/doc/
H A DREADME.mpc85xx-spin-table4 DDR is initialized and U-Boot relocates itself into DDR, the spin table is
5 accessible for core 0. It is part of release.S, within 4KB range after
6 __secondary_start_page. For other cores to use the spin table, the booting
9 Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
10 is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of
12 page translation for secondary cores to use this page of memory. Then 4KB
17 that secondary cores can see it.
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
H A DREADME.Heterogeneous-SoCs5 configuration and frequencies of all PowerPC cores and devices
7 SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc.
10 Heterogeneous SoCs which are chasis-2 compliant like B4860 and B4420
17 - arch/powerpc/cpu/mpc85xx/cpu.c
19 Code added in this file to print the DSP cores and other device's(CPRI,
22 - arch/powerpc/cpu/mpc85xx/speed.c
25 required cores and devices from RCW and System frequency
27 - arch/powerpc/cpu/mpc8xxx/cpu.c
29 Added API to get the number of SC cores in running system and Their BIT
32 - arch/powerpc/include/asm/config_mpc85xx.h
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/openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-power.json82 "BriefDescription": "Core 4 C State Transition Cycles",
130 "BriefDescription": "Deep C State Rejection - Core 0",
138 "BriefDescription": "Deep C State Rejection - Core 1",
146 "BriefDescription": "Deep C State Rejection - Core 10",
154 "BriefDescription": "Deep C State Rejection - Core 11",
162 "BriefDescription": "Deep C State Rejection - Core 12",
170 "BriefDescription": "Deep C State Rejection - Core 13",
178 "BriefDescription": "Deep C State Rejection - Core 14",
186 "BriefDescription": "Deep C State Rejection - Core 2",
194 "BriefDescription": "Deep C State Rejection - Core 3",
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/openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-power.json158 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
166 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
174 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
182 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
190 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
198 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
206 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
214 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
222 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
230 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
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/openbmc/qemu/docs/system/arm/
H A Draspi.rst8 ARM1176JZF-S core, 512 MiB of RAM
10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
19 -------------------
21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU
27 * Serial ports (BCM2835 AUX - 16550 based - and PL011)
41 ---------------
/openbmc/qemu/docs/system/s390x/
H A Dcpu-topology.rst1 .. _cpu-topology-s390x:
8 tree-shaped hierarchy.
13 - CPU type
14 - entitlement
15 - dedication
17 Each bit set in the bitmap correspond to a core-id of a vCPU with matching
23 monitor polarization changes, see ``docs/devel/s390-cpu-topology.rst``.
26 -------------
31 The s390x host needs to use a Linux kernel v6.0 or newer (which provides the so-called
33 CPU topology facility via the so-called STFLE bit 11 to the VM).
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/openbmc/linux/tools/power/cpupower/man/
H A Dcpupower.13 cpupower \- Shows and sets processor power related values
6 .B cpupower [ \-c cpulist ] <command> [ARGS]
8 .B cpupower \-v|\-\-version
10 .B cpupower \-h|\-\-help
16 The manpages of the commands (cpupower\-<command>(1)) provide detailed
22 \-\-help, \-h
23 .RS 4
27 \-\-cpu cpulist, \-c cpulist
28 .RS 4
29 Only show or set values for specific cores.
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H A Dcpupower-idle-set.11 .TH "CPUPOWER-IDLE-SET" "1" "0.1" "" "cpupower Manual"
4 cpupower\-idle\-set \- Utility to set cpu idle state specific kernel options
7 cpupower [ \-c cpulist ] idle\-set [\fIoptions\fP]
10 The cpupower idle\-set subcommand allows to set cpu idle, also called cpu
16 \fB\-d\fR \fB\-\-disable\fR <STATE_NO>
19 \fB\-e\fR \fB\-\-enable\fR <STATE_NO>
22 \fB\-D\fR \fB\-\-disable-by-latency\fR <LATENCY>
27 \fB\-E\fR \fB\-\-enable-all\fR
34 .RS 4
52 .RS 4
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H A Dcpupower-monitor.11 .TH CPUPOWER\-MONITOR "1" "22/02/2011" "" "cpupower Manual"
3 cpupower\-monitor \- Report processor frequency and idle statistics
7 .RB "\-l"
10 .RB [ -c ] [ "\-m <mon1>," [ "<mon2>,..." ] ]
11 .RB [ "\-i seconds" ]
14 .RB [ -c ][ "\-m <mon1>," [ "<mon2>,..." ] ]
18 \fBcpupower-monitor \fP reports processor topology, frequency and idle power
22 \fBcpupower-monitor \fP implements independent processor sleep state and
24 directly reading out hardware registers. Use \-l to get an overview which are
29 \-l
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H A Dcpupower-set.11 .TH CPUPOWER\-SET "1" "22/02/2011" "" "cpupower Manual"
3 cpupower\-set \- Set processor power related kernel or hardware configurations
6 .B cpupower set [ \-b VAL ]
13 Some options are platform wide, some affect single cores. By default values
14 are applied on all cores. How to modify single core configurations is
15 described in the cpupower(1) manpage in the \-\-cpu option section. Whether an
16 option affects the whole system or can be applied to individual cores is
24 \-\-perf-bias, \-b
25 .RS 4
30 The range of valid numbers is 0-15, where 0 is maximum
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
49 - const: arm,vexpress,v2p-ca9
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/openbmc/linux/drivers/crypto/cavium/cpt/
H A Dcptpf_main.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #define DRV_NAME "thunder-cpt"
19 static u32 num_vfs = 4; /* Default 4 VF enabled */
21 MODULE_PARM_DESC(num_vfs, "Number of VFs to enable(1-16)");
24 * Disable cores specified by coremask
32 struct device *dev = &cpt->pdev->dev; in cpt_disable_cores()
35 coremask = (coremask << cpt->max_se_cores); in cpt_disable_cores()
37 /* Disengage the cores from groups */ in cpt_disable_cores()
38 grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); in cpt_disable_cores()
39 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), in cpt_disable_cores()
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/openbmc/linux/arch/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 source "arch/arc/plat-hsdk/Kconfig"
102 The original ARC ISA of ARC600/700 cores
108 ISA for the Next Generation ARC-HS cores
126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
128 -Caches: New Prog Model, Region Flush
129 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
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/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-cache.json111 "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
115 …"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD…
210 "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
214 …"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 A…
309 "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
313 …"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL…
408 "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
412 …"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 B…
507 "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
511 …"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD…
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc6 4. LS1012A
13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
15 processor cores with datapath acceleration optimized for L2/3 packet
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
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/openbmc/linux/drivers/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
63 # 64-bit ARM SoCs
75 Tegra124's "4+1" Cortex-A15 CPU complex.
85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
86 cores in a switched configuration. It features a GPU of the Maxwell
88 and providing 256 CUDA cores. It supports hardware-accelerated en-
90 VP8 at 4K resolution and up to 60 fps.
106 combination of Denver and Cortex-A57 CPU cores and a GPU based on
107 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
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/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
29 #size-cells = <1>;
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/openbmc/linux/Documentation/admin-guide/device-mapper/
H A Dunstriped.rst2 Device-mapper "unstriped" target
8 The device-mapper "unstriped" target provides a transparent mechanism to
9 unstripe a device-mapper "striped" target to access the underlying disks
10 without having to touch the true backing block-device. It can also be
11 used to unstripe a hardware RAID-0 to access backing disks.
33 An example of undoing an existing dm-stripe
34 -------------------------------------------
36 This small bash script will setup 4 loop devices and use the existing
37 striped target to combine the 4 devices into one. It then will use
46 NUM=4
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/openbmc/linux/Documentation/arch/x86/
H A Dtopology.rst1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
24 threads, cores, packages, etc.
35 - packages
36 - cores
37 - threads
41 Packages contain a number of cores plus shared resources, e.g. DRAM
48 Package-related topology information in the kernel:
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/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-cache.json8 …"PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the nu…
18 …"PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the nu…
23 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
28 …"PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the nu…
38 …"PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the nu…
49 …"PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the nu…
91 "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
95 …"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD…
190 "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
194 …"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 A…
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-consumer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
25 $ref: /schemas/types.yaml#/definitions/phandle-array
32 firmware-name:
33 $ref: /schemas/types.yaml#/definitions/string-array
37 firmwares for the PRU cores, the default firmware for the core from
39 correspond to the PRU cores listed in the 'ti,prus' property
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