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/openbmc/u-boot/arch/arm/include/asm/mach-imx/
H A Dregs-common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
20 * 2) Set bits only access. To set bits, write which bits you want to set to the
22 * 3) Clear bits only access. To clear bits, write which bits you want to clear
24 * 4) Toggle bits only access. To toggle bits, write which bits you want to
27 * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
29 * explicitly set/cleared by using access type 2-3.
39 uint8_t name[4]; \
40 uint8_t name##_set[4]; \
41 uint8_t name##_clr[4]; \
42 uint8_t name##_tog[4]; \
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
10 * information contained in the core-isa.h header file.
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
25 /* Copyright (c) 1999-2020 Tensilica Inc.
49 /*----------------------------------------------------------------------
51 ----------------------------------------------------------------------*/
55 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
117 #define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */
118 #define XCHAL_CA_WRITEBACK 7 /* cache enabled (write-back) mode */
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/openbmc/u-boot/board/armltd/integrator/
H A Dpci_v3.h1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
13 /* -------------------------------------------------------------------------------
15 * -------------------------------------------------------------------------------
76 /* PCI COMMAND REGISTER bits
85 /* SYSTEM REGISTER bits
90 /* PCI_CFG bits
100 /* PCI_BASE register bits (PCI -> Local Bus)
108 /* PCI MAP register bits (PCI -> Local bus)
118 #define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4)
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/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2023 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
10 * https://github.com/riscv-non-isa/riscv-iommu
19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
23 * struct riscv_iommu_fq_record - Fault/Event Queue Record
40 * struct riscv_iommu_pq_record - PCIe Page Request record
64 #define RISCV_IOMMU_QUEUE_LOGSZ_FIELD GENMASK_ULL(4, 0)
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/openbmc/qemu/tests/functional/
H A Dtest_mem_addr_space.py11 # SPDX-License-Identifier: GPL-2.0-or-later
23 # This helper can go away when the 32-bit host deprecation
27 ident = fh.read(4)
31 # Non-ELF file implies macOS or Windows which
32 # we already assume to be 64-bit only
35 # bits == 1 -> 32-bit; bits == 2 -> 64-bit
36 bits = int.from_bytes(fh.read(1), byteorder='little')
37 if bits != 2:
38 # 32-bit ELF builds won't be able to address sufficient
40 self.skipTest("64-bit build host is required")
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/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dtimer.h1 /* SPDX-License-Identifier: GPL-2.0+ */
8 /* Each timer has 4 control bits in ctrl1 register.
9 * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
10 * such that timer X uses bits (4 * X - 4):(4 * X - 1)
11 * If the timer does not support PWM, bit 4 is reserved.
19 #define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1))
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dtimer.h1 /* SPDX-License-Identifier: GPL-2.0+ */
19 u32 mr[4]; /* Match Registers */
21 u32 cr[4]; /* Capture Registers */
27 /* Timer/Counter Interrupt Register bits */
28 #define TIMER_IR_CR(n) (1 << ((n) + 4))
31 /* Timer/Counter Timer Control Register bits */
36 /* Timer/Counter Match Control Register bits */
41 /* Timer/Counter Capture Control Register bits */
46 /* Timer/Counter External Match Register bits */
47 #define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4))
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/openbmc/u-boot/drivers/spi/
H A Datmel_spi.h14 #define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x))
17 /* Bits in CR */
23 /* Bits in MR */
28 #define ATMEL_SPI_MR_MODFDIS BIT(4)
34 /* Bits in RDR */
38 /* Bits in TDR */
43 /* Bits in SR/IER/IDR/IMR */
48 #define ATMEL_SPI_SR_ENDRX BIT(4)
56 /* Bits in CSRx */
60 #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
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/openbmc/qemu/audio/
H A Dwavcapture.c2 #include "qemu/qemu-print.h"
4 #include "qemu/error-report.h"
12 int bits; member
36 uint8_t rlen[4]; in wav_destroy()
37 uint8_t dlen[4]; in wav_destroy()
38 uint32_t datalen = wav->bytes; in wav_destroy()
41 if (wav->f) { in wav_destroy()
42 le_store (rlen, rifflen, 4); in wav_destroy()
43 le_store (dlen, datalen, 4); in wav_destroy()
45 if (fseek (wav->f, 4, SEEK_SET)) { in wav_destroy()
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/openbmc/u-boot/include/
H A Dmvmfp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
21 * MFP configuration is represented by a 32-bit unsigned integer
25 /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \
26 /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \
27 /* bit 12..11 - Driver Strength */ (((_drv) & 0x3) << 11) | \
28 /* bits 10 - pad driver */ (((_slp) & 0x1) << 10) | \
29 /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \
30 /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \
31 /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \
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/openbmc/intel-ipmi-oem/src/
H A Dipmi_to_redfish_hooks.cpp8 // http://www.apache.org/licenses/LICENSE-2.0
78 // error = eventData2 bits [3:0] in biosMessageHook()
81 // mode = eventData3 bits [3:0] in biosMessageHook()
140 // post LSB = eventData2 bits [7:0] in biosMessageHook()
142 // post MSB = eventData3 bits [7:0] in biosMessageHook()
176 // Node ID = eventData2 bits [7:0] in biosMessageHook()
208 // prior mode = eventData2 bits [3:0] in biosMessageHook()
211 // selected mode = eventData3 bits [3:0] in biosMessageHook()
348 // pair = eventData2 bits [7:4] in biosSMIMessageHook()
349 int pair = selData.eventData2 >> 4 & 0x0F; in biosSMIMessageHook()
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/openbmc/u-boot/arch/arm/dts/
H A Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
15 compatible = "socionext,uniphier-ld20";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&gic>;
21 #address-cells = <2>;
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H A Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
23 next-level-cache = <&l2>;
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H A Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
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/openbmc/qemu/target/hexagon/
H A Dcpu_bits.h2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
23 #define PCALIGN 4
24 #define PCALIGN_MASK (PCALIGN - 1)
27 HEX_EVENT_NONE = -1,
32 HEX_CAUSE_NONE = -1,
42 #define PACKET_WORDS_MAX 4
46 /* The parse bits are [15:14] */ in parse_bits()
52 /* The instruction class is encoded in bits [31:28] */ in iclass_bits()
53 uint32_t iclass = extract32(encoding, 28, 4); in iclass_bits()
54 /* If parse bits are zero, this is a duplex */ in iclass_bits()
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/openbmc/qemu/target/arm/
H A Dcpu.h23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-common.h"
28 #include "exec/cpu-defs.h"
29 #include "exec/cpu-interrupt.h"
31 #include "exec/page-protection.h"
32 #include "qapi/qapi-types-common.h"
35 #include "target/arm/cpu-sysregs.h"
40 #define EXCP_DATA_ABORT 4
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/openbmc/qemu/scripts/kvm/
H A Dvmxcap5 # Copyright 2009-2010 Red Hat, Inc.
11 # the COPYING file in the top-level directory.
44 def __init__(self, name, bits, cap_msr, true_cap_msr = None): argument
46 self.bits = bits
59 for bit in sorted(self.bits.keys()):
74 print(' %-40s %s' % (self.bits[bit], s))
76 # All 64 bits in the tertiary controls MSR are allowed-1
84 def __init__(self, name, bits, msr): argument
86 self.bits = bits
97 for bits in sorted(self.bits.keys(), key = first_bit):
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/openbmc/u-boot/drivers/video/
H A Dmvebu_lcd.c1 // SPDX-License-Identifier: GPL-2.0+
16 #define MVEBU_LCD_WIN_CONTROL(w) (0xf000 + ((w) << 4))
17 #define MVEBU_LCD_WIN_BASE(w) (0xf004 + ((w) << 4))
18 #define MVEBU_LCD_WIN_REMAP(w) (0xf00c + ((w) << 4))
113 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()
114 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_lcd_conf_mbus_registers()
115 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in mvebu_lcd_conf_mbus_registers()
116 (dram->mbus_dram_target_id << 4) | 1, in mvebu_lcd_conf_mbus_registers()
119 writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i)); in mvebu_lcd_conf_mbus_registers()
128 int x = lcd_info->x_res; in mvebu_lcd_register_init()
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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Ddavinci_nand.c1 // SPDX-License-Identifier: GPL-2.0+
18 * ----------------------------------------------------------------------------
20 * ----------------------------------------------------------------------------
28 -
34 #include <asm/ti-common/davinci_nand.h>
36 /* Definitions for 4-bit hardware ECC */
47 * Exploit the little endianness of the ARM to do multi-byte transfers
57 const u32 *nand = chip->IO_ADDR_R; in nand_davinci_read_buf()
65 len--; in nand_davinci_read_buf()
73 len -= 2; in nand_davinci_read_buf()
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/openbmc/qemu/include/standard-headers/drm/
H A Ddrm_fourcc.h38 * further describe the buffer's format - for example tiling or compression.
41 * ----------------
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * may preserve meaning - such as number of planes - from the fourcc code,
63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
75 * - Kernel and user-space drivers: for drivers it's important that modifiers
79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
92 * -----------------------
97 * upstream in-kernel or open source userspace user does not apply.
115 #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
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/openbmc/qemu/include/
H A Delf.h4 /* 32-bit ELF base types. */
11 /* 64-bit ELF base types. */
26 #define PT_NOTE 4
47 #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
48 #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
49 #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
50 #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
51 #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
88 #define EF_MIPS_MACH_SB1 0x008a0000 /* Broadcom SB-1 */
96 #define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra RM9000 */
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/openbmc/qemu/target/i386/kvm/
H A Dhyperv-proto.h2 * Definitions for Hyper-V guest/hypervisor interaction - x86-specific part
4 * Copyright (c) 2017-2018 Virtuozzo International GmbH.
7 * See the COPYING file in the top-level directory.
13 #include "hw/hyperv/hyperv-proto.h"
30 * HV_CPUID_FEATURES.EAX bits
36 #define HV_APIC_ACCESS_AVAILABLE (1u << 4)
45 * HV_CPUID_FEATURES.EBX bits
47 #define HV_POST_MESSAGES (1u << 4)
51 * HV_CPUID_FEATURES.EDX bits
57 #define HV_HYPERCALL_XMM_INPUT_AVAILABLE (1u << 4)
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/openbmc/u-boot/drivers/mtd/ubi/
H A Dcrc32.c5 * subsequently included in the kernel, thus was re-licensed under the
55 * crc32_le() - Calculate bitwise little-endian Ethernet AUTODIN II CRC32
65 * In fact, the table-based code will work in this case, but it can be
72 while (len--) { in crc32_le()
79 #else /* Table-based approach */
100 } while ((--len) && ((long)b)&3 ); in crc32_le()
102 if((len >= 4)){ in crc32_le()
103 /* load data 32 bits wide, xor data 32 bits wide. */ in crc32_le()
106 --b; /* use pre increment below(*++b) for speed */ in crc32_le()
113 } while (--len); in crc32_le()
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/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/meta-python/recipes-connectivity/lirc/lirc/
H A Dlircd.conf10 bits 8
41 4 0xC0
70 # brand: STM PVR-1
74 bits 16
96 4 0xe01f
141 # brand: STM DTV-2
147 bits 13
163 4 0x1004
211 # 32 bits for the pre-date (should be value 0x170F443E)
214 # 24 bits for the data (key code)
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/openbmc/u-boot/board/freescale/mpc832xemds/
H A DREADME2 -----------------------------------------
4 1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
9 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
10 bits may contribute to signals that are numbered based at 0,
11 and some of those signals may be high-bit-number-0 too. Heed
17 SW3 is switch 18 as silk-screened onto the board.
18 SW4[8] is the bit labeled 8 on Switch 4.
19 SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
20 SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
21 SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
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