| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-srggb10-ipu3.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-pix-fmt-ipu3-sbggr10:
4 .. _v4l2-pix-fmt-ipu3-sgbrg10:
5 .. _v4l2-pix-fmt-ipu3-sgrbg10:
6 .. _v4l2-pix-fmt-ipu3-srggb10:
13 10-bit Bayer formats
20 sRGB / Bayer formats with 10 bits per sample with every 25 pixels packed
21 to 32 bytes leaving 6 most significant bits padding in the last byte.
24 In other respects this format is similar to :ref:`V4L2-PIX-FMT-SRGGB10`.
36 .. flat-table::
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| H A D | pixfmt-srggb14p.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB14P:
4 .. _v4l2-pix-fmt-sbggr14p:
5 .. _v4l2-pix-fmt-sgbrg14p:
6 .. _v4l2-pix-fmt-sgrbg14p:
17 14-bit packed Bayer formats
24 bits per colour. Every four consecutive samples are packed into seven
25 bytes. Each of the first four bytes contain the eight high order bits
27 significants bits of each pixel, in the same order.
29 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
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| H A D | pixfmt-packed-yuv.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-yuv:
15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
18 denotes bits of the alpha component (if supported by the format), and 'X'
19 denotes padding bits.
22 4:4:4 Subsampling
28 The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
30 seen in a 16-bit word, which is then stored in memory in little endian byte
31 order, and on the number of bits for each component. For instance the YUV565
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| /openbmc/linux/drivers/crypto/hisilicon/sec2/ |
| H A D | sec_crypto.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
99 * mac_len: 0~4 bits
100 * a_key_len: 5~10 bits
101 * a_alg: 11~16 bits
106 * c_icv_len: 0~5 bits
107 * c_width: 6~8 bits
108 * c_key_len: 9~11 bits
109 * c_mode: 12~15 bits
113 /* c_alg: 0~3 bits */
118 * a_len: 0~23 bits
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| /openbmc/linux/include/rdma/ |
| H A D | ib_smi.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
71 u8 linkspeed_portstate; /* 4 bits, 4 bits */
72 u8 portphysstate_linkdown; /* 4 bits, 4 bits */
73 u8 mkeyprot_resv_lmc; /* 2 bits, 3, 3 */
74 u8 linkspeedactive_enabled; /* 4 bits, 4 bits */
75 u8 neighbormtu_mastersmsl; /* 4 bits, 4 bits */
76 u8 vlcap_inittype; /* 4 bits, 4 bits */
80 u8 inittypereply_mtucap; /* 4 bits, 4 bits */
81 u8 vlstallcnt_hoqlife; /* 3 bits, 5 bits */
82 u8 operationalvl_pei_peo_fpi_fpo; /* 4 bits, 1, 1, 1, 1 */
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| H A D | opa_port_info.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright (c) 2014-2020 Intel Corporation. All rights reserved.
12 #define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */
17 #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
23 #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
24 #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
31 #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4
61 /* 34 -reserved */
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| /openbmc/linux/drivers/pci/ |
| H A D | pci-bridge-emul.c | 1 // SPDX-License-Identifier: GPL-2.0
21 #include "pci-bridge-emul.h"
28 * struct pci_bridge_reg_behavior - register bits behaviors
29 * @ro: Read-Only bits
30 * @rw: Read-Write bits
31 * @w1c: Write-1-to-Clear bits
33 * Reads and Writes will be filtered by specified behavior. All other bits not
36 * multi-bit fields) when read".
39 /* Read-only bits */
42 /* Read-write bits */
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| /openbmc/linux/tools/edid/ |
| H A D | edid.S | 18 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
36 /* Provide defaults for the timing bits */
48 ((((v1-'@')&0x1f)<<10)+(((v2-'@')&0x1f)<<5)+((v3-'@')&0x1f))
50 #define lsbs2(v1,v2) (((v1&0x0f)<<4)+(v2&0x0f))
51 #define msbs2(v1,v2) ((((v1>>8)&0x0f)<<4)+((v2>>8)&0x0f))
53 ((((v1>>8)&0x03)<<6)+(((v2>>8)&0x03)<<4)+\
54 (((v3>>4)&0x03)<<2)+((v4>>4)&0x03))
68 /* Serial number. 32 bits, little endian. */
74 /* Year of manufacture, less 1990. (1990-2245)
76 year: .byte YEAR-1990
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| /openbmc/linux/drivers/gpu/drm/gma500/ |
| H A D | oaktrail.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2007-2011, Intel Corporation.
16 u8 hblank_hi:4;
17 u8 hactive_hi:4;
20 u8 vblank_hi:4;
21 u8 vactive_hi:4;
24 u8 vsync_pulse_width_lo:4;
25 u8 vsync_offset_lo:4;
32 u8 height_mm_hi:4;
33 u8 width_mm_hi:4;
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| /openbmc/linux/include/drm/display/ |
| H A D | drm_dsc.h | 1 /* SPDX-License-Identifier: MIT
28 #define DSC_PPS_VERSION_MAJOR_SHIFT 4
29 #define DSC_PPS_BPC_SHIFT 4
35 #define DSC_PPS_CONVERT_RGB_SHIFT 4
39 #define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4
48 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
64 * Bits/group offset to apply to target for this group
70 * struct drm_dsc_config - Parameters required to configure DSC
78 * Bits per component for previous reconstructed line buffer
82 * @bits_per_component: Bits per component to code (8/10/12)
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| /openbmc/linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | socionext,uniphier-efuse.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/socionext,uniphier-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Keiji Hayashibara <hayashibara.keiji@socionext.com>
11 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
14 - $ref: nvmem.yaml#
18 const: socionext,uniphier-efuse
24 - compatible
25 - reg
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| /openbmc/linux/include/linux/irqchip/ |
| H A D | irq-bcm2836.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
13 * next 2 bits identify the CPU that the GPU FIQ goes to.
16 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
18 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
21 * The low 4 bits of this are the CPU's timer IRQ enables, and the
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
23 * bits).
27 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
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| /openbmc/linux/drivers/iio/dac/ |
| H A D | ad5686.c | 1 // SPDX-License-Identifier: GPL-2.0
33 return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1; in ad5686_get_powerdown_mode()
42 st->pwr_down_mode &= ~(0x3 << (chan->channel * 2)); in ad5686_set_powerdown_mode()
43 st->pwr_down_mode |= ((mode + 1) << (chan->channel * 2)); in ad5686_set_powerdown_mode()
60 return sysfs_emit(buf, "%d\n", !!(st->pwr_down_mask & in ad5686_read_dac_powerdown()
61 (0x3 << (chan->channel * 2)))); in ad5686_read_dac_powerdown()
81 st->pwr_down_mask |= (0x3 << (chan->channel * 2)); in ad5686_write_dac_powerdown()
83 st->pwr_down_mask &= ~(0x3 << (chan->channel * 2)); in ad5686_write_dac_powerdown()
85 switch (st->chip_info->regmap_type) { in ad5686_write_dac_powerdown()
98 if (chan->channel > 0x7) in ad5686_write_dac_powerdown()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dp_types.h | 36 LANE_COUNT_FOUR = 4,
50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
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| /openbmc/linux/lib/xz/ |
| H A D | xz_lzma2.h | 5 * Igor Pavlov <https://7-zip.org/>
24 * number of bits of the current uncompressed offset. In some places there
27 #define POS_STATES_MAX (1 << 4)
34 * - Literal: One 8-bit byte
35 * - Match: Repeat a chunk of data at some distance
36 * - Long repeat: Multi-byte match at a recently seen distance
37 * - Short repeat: One-byte repeat at a recently seen distance
40 * either short or long repeated match, and NONLIT means any non-literal.
69 *state -= 3; in lzma_state_literal()
71 *state -= 6; in lzma_state_literal()
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| /openbmc/linux/drivers/net/ipa/reg/ |
| H A D | ipa_reg-v3.5.1.c | 1 // SPDX-License-Identifier: GPL-2.0
15 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
16 /* Bits 5-31 reserved */
26 [RAM_ARB] = BIT(4),
44 /* Bits 22-31 reserved */
55 /* Bits 22-23 reserved */
57 /* Bits 25-31 reserved */
71 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
72 /* Bits 8-31 reserved */
79 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
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| H A D | ipa_reg-v4.2.c | 1 // SPDX-License-Identifier: GPL-2.0
15 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
29 /* Bits 21-31 reserved */
39 [RAM_ARB] = BIT(4),
65 /* Bits 30-31 reserved */
76 /* Bits 22-23 reserved */
78 /* Bits 25-31 reserved */
92 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
93 /* Bits 8-31 reserved */
100 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
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| H A D | ipa_reg-v4.7.c | 1 // SPDX-License-Identifier: GPL-2.0
15 /* Bit 4 reserved */
30 /* Bits 22-31 reserved */
40 [RAM_ARB] = BIT(4),
78 /* Bits 22-23 reserved */
80 /* Bits 25-31 reserved */
94 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
95 /* Bits 8-31 reserved */
102 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
103 /* Bits 8-15 reserved */
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| H A D | ipa_reg-v4.11.c | 1 // SPDX-License-Identifier: GPL-2.0
15 /* Bit 4 reserved */
34 /* Bits 24-29 reserved */
46 [RAM_ARB] = BIT(4),
84 /* Bits 22-23 reserved */
86 /* Bits 25-31 reserved */
100 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
101 /* Bits 8-31 reserved */
108 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
109 /* Bits 8-15 reserved */
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| H A D | ipa_reg-v4.9.c | 1 // SPDX-License-Identifier: GPL-2.0
15 /* Bit 4 reserved */
33 /* Bits 25-29 reserved */
45 [RAM_ARB] = BIT(4),
83 /* Bits 22-23 reserved */
85 /* Bits 25-31 reserved */
99 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
100 /* Bits 8-31 reserved */
107 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
108 /* Bits 8-15 reserved */
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| /openbmc/qemu/target/xtensa/core-de233_fpu/ |
| H A D | core-matmap.h | 2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
10 * information contained in the core-isa.h header file.
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
25 /* Copyright (c) 1999-2020 Tensilica Inc.
49 /*----------------------------------------------------------------------
51 ----------------------------------------------------------------------*/
55 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
117 #define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */
118 #define XCHAL_CA_WRITEBACK 7 /* cache enabled (write-back) mode */
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| /openbmc/linux/drivers/net/ieee802154/ |
| H A D | mcr20a.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
50 /*------------------ 0x27 */
69 /*----------------------- 0x3A */
118 /*-------------------- 0x29 */
124 /*------------------ 0x2F */
128 /*------------------- 0x33 */
147 /*-------------------- 0x46 */
163 /*------------------- 0x56 */
164 /*------------------- 0x57 */
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| /openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | tda1997x.txt | 1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
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| /openbmc/linux/drivers/dma/idxd/ |
| H A D | registers.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define GET_IDXD_VER_MAJOR(x) (((x) & IDXD_VER_MAJOR_MASK) >> 4)
37 u64 max_batch_shift:4;
42 u64 bits; member
50 u64 wqcfg_size:4;
62 u64 bits; member
76 u64 bits; member
85 u64 bits; member
94 u64 bits[4]; member
111 u64 bits[2]; member
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| /openbmc/linux/lib/ |
| H A D | crc4.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * crc4.c - simple crc-4 calculations.
15 * crc4 - calculate the 4-bit crc of a value.
18 * @bits: number of bits in @x to checksum
22 * The @x value is treated as left-aligned, and bits above @bits are ignored
25 uint8_t crc4(uint8_t c, uint64_t x, int bits) in crc4() argument
30 x &= (1ull << bits) - 1; in crc4()
32 /* Align to 4-bits */ in crc4()
33 bits = (bits + 3) & ~0x3; in crc4()
35 /* Calculate crc4 over four-bit nibbles, starting at the MSbit */ in crc4()
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