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/openbmc/linux/arch/parisc/include/asm/
H A Dassembly.h26 /* Frame alignment for 32- and 64-bit */
62 #define LDREGM ldd,mb
136 zdep \r, 31-(\sa), 32-(\sa), \t
144 /* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
146 extru \r, 31-(\sa), 32-(\sa), \t
154 /* Extract unsigned for 32- and 64-bit
155 * The extru instruction leaves the most significant 32 bits of the
159 extrd,u \r, 32+(\p), \len, \t
165 /* The depi instruction leaves the most significant 32 bits of the
169 depdi \i, 32+(\p), \len, \t
[all …]
/openbmc/u-boot/doc/
H A DREADME.b4860qds45 . 32 Kbyte L1 ICache per e6500/SC3900 core
46 . 32 Kbyte L1 DCache per e6500/SC3900 core
61 . 182 32-bit timers
172 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
174 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
176 0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
177 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
178 0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
180 0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
181 0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
[all …]
H A DREADME.N12137 - 16-/32-bit mixable instruction format.
8 - 32 general-purpose 32-bit registers.
11 - 32/64/128/256 BTB.
23 - 32/64/128-entry 4-way set-associati.ve main TLB.
27 - 4KB & 1MB.
28 - 8KB & 1MB.
33 - Cache size: 8KB/16KB/32KB/64KB.
34 - Cache line size: 16B/32B.
38 - Size: 4KB to 1MB.
/openbmc/linux/Documentation/admin-guide/cgroup-v1/
H A Dhugetlb.rst34 For a system supporting three hugepage sizes (64k, 32M and 1G), the control
55 hugetlb.32MB.limit_in_bytes
56 hugetlb.32MB.max_usage_in_bytes
57 hugetlb.32MB.numa_stat
58 hugetlb.32MB.usage_in_bytes
59 hugetlb.32MB.failcnt
60 hugetlb.32MB.rsvd.limit_in_bytes
61 hugetlb.32MB.rsvd.max_usage_in_bytes
62 hugetlb.32MB.rsvd.usage_in_bytes
63 hugetlb.32MB.rsvd.failcnt
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
57 - 32-bit RISC controller for flexible support of the communications peripherals
71 DDR: 64-bit 32-bit
72 IFC: 32-bit 28-bit
87 - NOR: 128MB 16-bit NOR Flash
96 - On-board 64MB SPI flash
107 - SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
115 - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
116 - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
117 - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
[all …]
/openbmc/u-boot/board/freescale/ls1046ardb/
H A DREADME29 - One 512 MB NAND flash with ECC support
34 - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
44 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
45 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
48 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
55 0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
56 0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
57 0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
61 0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB
62 0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
[all …]
/openbmc/linux/arch/x86/kernel/
H A Dearly-quirks.c243 #define MB(x) (KB (KB (x))) macro
253 return MB(1); in i830_tseg_size()
268 case I845_TSEG_SIZE_1M: return MB(1); in i845_tseg_size()
282 return MB(1); in i85x_tseg_size()
287 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32); in i830_mem_size()
292 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32); in i85x_mem_size()
349 bsm |= (u64)read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW1) << 32; in gen11_stolen_base()
364 case I830_GMCH_GMS_STOLEN_1024: return MB(1); in i830_stolen_size()
365 case I830_GMCH_GMS_STOLEN_8192: return MB(8); in i830_stolen_size()
384 case I855_GMCH_GMS_STOLEN_1M: return MB(1); in gen3_stolen_size()
[all …]
/openbmc/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Dfq_codel.json18 …]+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
41 …9]+ limit 1000p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
87 …]+ limit 10240p flows 1024 quantum.*target 2ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
110 …-9]+ limit 10240p flows 1024 quantum.*target 5ms interval 5ms memory_limit 32Mb ecn drop_batch 64",
133 …imit 10240p flows 1024 quantum 9000 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
156 …[0-9]+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb drop_batch 64",
179 …ws 1024 quantum.*target 5ms ce_threshold 1.02s interval 100ms memory_limit 32Mb ecn drop_batch 64",
202 …+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 100",
225 …9]+ limit 1000p flows 256 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 100",
249 … [0-9]+ limit 1000p flows 256 quantum.*target 5ms interval 100ms memory_limit 32Mb drop_batch 100",
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi.h15 #define SRAM_BAR_SIZE 0x4000000ull /* 64MB */
16 #define CFG_BAR_SIZE 0x8000000ull /* 128MB */
19 #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
22 #define SRAM_SIZE 0x1400000 /* 20MB */
30 #define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */
37 #define GAUDI_MSI_ENTRIES 32
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2.h16 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
21 #define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/
22 #define CFG_REGION_SIZE 0xC000000ull /* 192MB */
24 #define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */
25 #define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */
26 #define STM_FLASH_SIZE 0x2000000ull /* 32MB */
29 #define SPI_FLASH_SIZE 0x1000000ull /* 16MB */
35 #define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */
38 #define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */
41 #define SRAM_SIZE 0x3000000ull /* 48MB */
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dsdram.c242 * 00000000 0000MB-1992MB 1992MB RAM (writeback) in sdram_find()
243 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) in sdram_find()
244 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) in sdram_find()
245 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) in sdram_find()
246 * 7f200000 2034MB TOLUD in sdram_find()
247 * 7f800000 2040MB MEBASE in sdram_find()
248 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) in sdram_find()
249 * 80000000 2048MB TOM in sdram_find()
250 * 100000000 4096MB-4102MB 6MB RAM (writeback) in sdram_find()
254 * 00000000 0000MB-2768MB 2768MB RAM (writeback) in sdram_find()
[all …]
/openbmc/u-boot/board/freescale/mpc8568mds/
H A Dlaw.c17 *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
18 *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
22 *5) 0xc000_0000 0xdfff_ffff SRIO 512MB
23 *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
24 *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
25 *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
26 *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
27 *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB
/openbmc/linux/Documentation/fb/
H A Dmatroxfb.rst53 32 0x112 0x183 0x115 0x18B
68 32 0x118 0x193 0x11B 0x19B
87 example 1600x1200x32bpp can be specified by `video=matroxfb:vesa:0x11C,depth:32`.
94 architectures there are some glitches for 24bpp videomodes. 8, 16 and 32bpp
128 memory usable for on-screen display (i.e. max. 8 MB).
143 transaction terminate with success or retry in 32 PCLK).
165 - 0 -> 2x128Kx32 chips, 2MB onboard, probably sgram
166 - 1 -> 2x128Kx32 chips, 4MB onboard, probably sgram
167 - 2 -> 2x256Kx32 chips, 4MB onboard, probably sgram
168 - 3 -> 2x256Kx32 chips, 8MB onboard, probably sgram
[all …]
H A Dintelfb.rst36 (default = 1024x768-32@70)
39 select amount of system RAM in MB to allocate for the video memory
42 Recommendation: 1 - 4 MB.
43 (default = 4 MB)
46 select at what offset in MB of the logical memory to allocate the
49 usage, adjust the value up or down, (0 for maximum usage, 63/127 MB
54 (default = 48 MB)
99 append="video=intelfb:mode=800x600-32@75,accel,hwcursor,vram=8"
101 This will initialize the framebuffer to 800x600 at 32bpp and 75Hz. The
102 framebuffer will use 8 MB of System RAM. hw acceleration of text and cursor
[all …]
/openbmc/linux/arch/mips/include/asm/sgi/
H A Dgio.h20 * There is 10MB of GIO address space for GIO64 slot devices
23 * 0 GFX 0x1f000000 - 0x1f3fffff 4MB
24 * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
25 * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
29 * - MISC 0x1fb00000 - 0x1fbfffff 1MB
32 * - RESERVED 0x18000000 - 0x1effffff 112MB
37 * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
41 * 32-bit IDs are divided into
44 * 1=GIO Product ID is 32 bits wide.
71 * [*] Device provide 32-bit ID.
/openbmc/linux/drivers/eisa/
H A Deisa.ids14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
50 ADI0001 "Lightning Networks 32-Bit EISA Ethernet LAN Adapter"
55 AIM0002 "AUVA OPTi/EISA 32-Bit 486 All-in-One System Board"
134 BUS4201 "BusTek/BusLogic Bt74xB 32-Bit Bus Master EISA-to-SCSI Host Adapter"
135 BUS4202 "BusTek/BusLogic Bt74xC 32-Bit Bus Master EISA-to-SCSI Host Adapter"
136 BUS6001 "BusTek/BusLogic Bt760 32-Bit Bus Master EISA-to-Ethernet Controller"
137 BUS6301 "BusTek/BusLogic Bt763E EISA 32-Bit 82596-based Ethernet Controller"
155 CNT2000 "900E/950E EISA Bus 32-bit Ethernet LAN Adapter"
158 COG9002 "Cogent eMASTER+ EISA XL 32-Bit Burst-mode Ethernet Adapter"
[all …]
/openbmc/u-boot/board/freescale/mpc8569mds/
H A Dlaw.c17 *1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
20 *3) 0xc000_0000 0xdfff_ffff SRIO 512MB
21 *4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
22 *4.b) 0xf800_0000 0xf800_7fff BCSR 32KB
23 *4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
24 *4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
25 *4.e) 0xfe00_0000 0xffff_ffff Flash 32MB
/openbmc/u-boot/board/freescale/t1040qds/
H A DREADME17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
66 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
101 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
106 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
107 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
108 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
109 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
110 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
111 0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
112 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
[all …]
/openbmc/u-boot/board/freescale/ls1046aqds/
H A DREADME25 - One in-socket 128 MB NOR flash 16-bit data bus
26 - One 512 MB NAND flash with ECC support
48 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
49 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
52 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
53 0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB
60 0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
61 0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
62 0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
/openbmc/u-boot/cmd/
H A Dotp_info.h55 { 12, 2, 0, "VGA memory size : 8MB" },
56 { 12, 2, 1, "VGA memory size : 16MB" },
57 { 12, 2, 2, "VGA memory size : 32MB" },
58 { 12, 2, 3, "VGA memory size : 64MB" },
85 { 32, 1, 0, "MAC 3 : RMII/NCSI" },
86 { 32, 1, 1, "MAC 3 : RGMII" },
111 { 45, 3, 0, "Boot SPI flash size : 0MB" },
112 { 45, 3, 1, "Boot SPI flash size : 2MB" },
113 { 45, 3, 2, "Boot SPI flash size : 4MB" },
114 { 45, 3, 3, "Boot SPI flash size : 8MB" },
[all …]
/openbmc/u-boot/arch/x86/
H A DKconfig8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
19 For now, 32-bit mode is recommended, as 64-bit is still
23 bool "32-bit"
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
41 runs through the 16-bit and 32-bit init, then switches to 64-bit
158 # The following options control where the 16-bit and 32-bit init lies
[all …]
/openbmc/linux/arch/powerpc/lib/
H A Dtest-code-patching.c62 /* Maximum positive relative branch, + 20MB - 4B */ in test_branch_iform()
68 /* Largest negative relative branch, - 32 MB */ in test_branch_iform()
87 /* Maximum relative negative offset, - 32 MB */ in test_branch_iform()
92 /* Out of range relative negative offset, - 32 MB + 4*/ in test_branch_iform()
96 /* Out of range relative positive offset, + 32 MB */ in test_branch_iform()
151 /* Maximum positive relative conditional branch, + 32 KB - 4B */ in test_branch_bform()
157 /* Largest negative relative conditional branch, - 32 KB */ in test_branch_bform()
179 /* Maximum relative negative offset, - 32 KB */ in test_branch_bform()
184 /* Out of range relative negative offset, - 32 KB + 4*/ in test_branch_bform()
188 /* Out of range relative positive offset, + 32 KB */ in test_branch_bform()
[all …]
/openbmc/linux/arch/x86/kernel/cpu/
H A Dcacheinfo.c53 #define MB(x) ((x) * 1024) macro
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
63 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
69 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
70 { 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
71 { 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
72 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
[all …]
/openbmc/u-boot/include/configs/
H A Dedb93xx.h104 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
108 * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
109 * 64 MB of SDRAM.
118 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
122 * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
141 (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
156 * data bus, for a total of 16 MB of CFI-compatible flash.
159 * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
160 * data bus, for a total of 32 MB of CFI-compatible flash.
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
57 - 32-bit RISC controller for flexible support of the communications peripherals
71 DDR: 64-bit 32-bit
72 IFC: 32-bit 28-bit
93 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
157 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
161 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
162 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
163 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
164 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
[all …]

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