1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2018-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay #ifndef GAUDI_H 9*e65e175bSOded Gabbay #define GAUDI_H 10*e65e175bSOded Gabbay 11*e65e175bSOded Gabbay #define SRAM_BAR_ID 0 12*e65e175bSOded Gabbay #define CFG_BAR_ID 2 13*e65e175bSOded Gabbay #define HBM_BAR_ID 4 14*e65e175bSOded Gabbay 15*e65e175bSOded Gabbay #define SRAM_BAR_SIZE 0x4000000ull /* 64MB */ 16*e65e175bSOded Gabbay #define CFG_BAR_SIZE 0x8000000ull /* 128MB */ 17*e65e175bSOded Gabbay 18*e65e175bSOded Gabbay #define CFG_BASE 0x7FFC000000ull 19*e65e175bSOded Gabbay #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/ 20*e65e175bSOded Gabbay 21*e65e175bSOded Gabbay #define SRAM_BASE_ADDR 0x7FF0000000ull 22*e65e175bSOded Gabbay #define SRAM_SIZE 0x1400000 /* 20MB */ 23*e65e175bSOded Gabbay 24*e65e175bSOded Gabbay #define SPI_FLASH_BASE_ADDR 0x7FF8000000ull 25*e65e175bSOded Gabbay 26*e65e175bSOded Gabbay #define PSOC_SCRATCHPAD_ADDR 0x7FFBFE0000ull 27*e65e175bSOded Gabbay #define PSOC_SCRATCHPAD_SIZE 0x10000 /* 64KB */ 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define PCIE_FW_SRAM_ADDR 0x7FFBFF0000ull 30*e65e175bSOded Gabbay #define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */ 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay #define DRAM_PHYS_BASE 0x0ull 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay #define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */ 35*e65e175bSOded Gabbay #define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */ 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define GAUDI_MSI_ENTRIES 32 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define MAX_ASID 2 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define PROT_BITS_OFFS 0xF80 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define MME_NUMBER_OF_MASTER_ENGINES 2 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define MME_NUMBER_OF_SLAVE_ENGINES 2 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define TPC_NUMBER_OF_ENGINES 8 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define DMA_NUMBER_OF_CHANNELS 8 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define NIC_NUMBER_OF_MACROS 5 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2) 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define NUMBER_OF_IF 8 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define DEVICE_CACHE_LINE_SIZE 128 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #endif /* GAUDI_H */ 62