| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | hw_data.c | 32 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
33 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
34 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
35 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
36 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
37 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
38 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
43 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
44 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
45 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | hw_data.c | 36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | maxim,max9485.txt | 5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
15 - clocks: Input clock, must provide 27.000 MHz
34 xo-27mhz: xo-27mhz {
45 clocks = <&xo-27mhz>;
|
| H A D | starfive,jh7100-clkgen.yaml | 22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
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| /openbmc/linux/drivers/clocksource/ |
| H A D | scx200_hrt.c | 5 * This is a clocksource driver for the Geode SCx200's 1 or 27 MHz
25 MODULE_PARM_DESC(mhz27, "count at 27.0 MHz (default is 1.0 MHz)");
36 #define HR_TMCLKSEL (1 << 1) /* 1|0 counts at 27|1 MHz */
39 /* The base timer frequency, * 27 if selected */
78 freq *= 27; in init_hrt_clocksource()
80 pr_info("enabling scx200 high-res timer (%s MHz +%d ppm)\n", mhz27 ? "27":"1", ppm); in init_hrt_clocksource()
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| /openbmc/qemu/include/hw/misc/ |
| H A D | aspeed_scu.h | 101 * 27 2D Engine GCLK clock source selection
131 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
148 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
150 * The default frequency is 792Mhz when CLKIN = 24MHz
160 * 28:27 DRAM size setting (for VGA driver use)
162 * 23 Enable 25 MHz reference clock input
185 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27)
186 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27)
267 * 27 Enable fast reset mode for ARM ICE debugger
271 * 23 Select 25 MHz reference clock input mode
[all …]
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| /openbmc/linux/Documentation/fb/ |
| H A D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/ |
| H A D | types.h | 21 #define SC_10MHZ 10000000U /* 10MHz */
22 #define SC_20MHZ 20000000U /* 20MHz */
23 #define SC_25MHZ 25000000U /* 25MHz */
24 #define SC_27MHZ 27000000U /* 27MHz */
25 #define SC_40MHZ 40000000U /* 40MHz */
26 #define SC_45MHZ 45000000U /* 45MHz */
27 #define SC_50MHZ 50000000U /* 50MHz */
28 #define SC_60MHZ 60000000U /* 60MHz */
29 #define SC_66MHZ 66666666U /* 66MHz */
30 #define SC_74MHZ 74250000U /* 74.25MHz */
[all …]
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| /openbmc/linux/drivers/media/pci/cx23885/ |
| H A D | netup-init.c | 95 /* set 27MHz on AUX_CLK */
104 /* Aux PLL frac for 27 MHz */ in netup_initialize()
107 /* Aux PLL int for 27 MHz */ in netup_initialize()
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| /openbmc/u-boot/doc/device-tree-bindings/rtc/ |
| H A D | brcm,brcmstb-waketimer.txt | 3 The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
12 - clocks : The phandle to the UPG fixed clock (27Mhz domain)
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | valkyriefb.h | 79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
[all …]
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | mxl5xx_defs.h | 396 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
397 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
398 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
399 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
404 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
433 MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
450 #define MXL_HYDRA_NCO_CLK 418 /* 418 MHz */
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/rtc/ |
| H A D | brcm,brcmstb-waketimer.yaml | 13 The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
38 description: clock reference in the 27MHz domain
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| /openbmc/linux/drivers/clk/spear/ |
| H A D | spear1340_clock.c | 20 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
32 #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
73 #define SPEAR1340_I2S_SCLK_X_SHIFT 27
106 #define SPEAR1340_CLCD_CLK_ENB 27
164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
[all …]
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| /openbmc/linux/drivers/media/tuners/ |
| H A D | qt1010_priv.h | 22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
54 27 29 ?
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
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| /openbmc/u-boot/arch/arm/mach-uniphier/clk/ |
| H A D | pll-ld4.c | 23 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ in upll_init()
31 /* AXO: 25MHz */ in upll_init()
35 /* AXO: default 24.576MHz */ in upll_init()
43 /* set 1 to K_LD(UPLLCTRL.bit[27]) */ in upll_init()
98 /* AXO: 25MHz */ in vpll_init()
108 /* AXO: default 24.576MHz */ in vpll_init()
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| /openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/ |
| H A D | rs.h | 14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
[all …]
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | clock.c | 647 ….lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 },…
649 ….lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, …
651 ….lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, …
653 ….lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }…
655 ….lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }…
657 ….lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }…
659 ….lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, …
665 ….lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }…
682 * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz, in clock_get_osc_freq()
683 * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz in clock_get_osc_freq()
[all …]
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| /openbmc/linux/tools/power/x86/x86_energy_perf_policy/ |
| H A D | x86_energy_perf_policy.8 | 119 is in units of 100 MHz, Eg. 12 signifies 1200 MHz.
146 level on this processor, specified in multiples of 100 MHz.
186 cpu0: HWP_CAP: low 1 eff 8 guar 27 high 35
189 cpu1: HWP_CAP: low 1 eff 8 guar 27 high 35
192 cpu2: HWP_CAP: low 1 eff 8 guar 27 high 35
195 cpu3: HWP_CAP: low 1 eff 8 guar 27 high 35
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 19 #define MT7623_PLL_FMAX (2000UL * MHZ)
20 #define MT7623_CON0_RST_BAR BIT(27)
83 FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
84 FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
85 FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
86 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
87 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
88 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
89 FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
90 FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | sony,imx412.yaml | 34 description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz
|
| H A D | sony,imx415.yaml | 31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
|
| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_stm32f.c | 31 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
59 #define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
70 #define RCC_DCKCFGRX_CK48MSEL BIT(27)
83 #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
104 /* 180 MHz */
118 /* 200 MHz */
184 /* select PLLSAIP as 48MHz clock source */ in configure_clocks()
187 /* select PLLQ as 48MHz clock source */ in configure_clocks()
190 /* select 48MHz as SDMMC1 clock source */ in configure_clocks()
193 /* select 48MHz as SDMMC2 clock source */ in configure_clocks()
[all …]
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 578 ….lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }…
580 ….lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, …
582 ….lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF…
584 ….lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF…
586 ….lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF…
588 ….lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF…
590 ….lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, …
594 ….lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF…
596 ….lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }…
849 * PLLC output frequency set to 600Mhz in clock_early_init()
[all …]
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| /openbmc/linux/arch/arm/mach-sa1100/include/mach/ |
| H A D | SA-1100.h | 262 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
263 * or 3.5795 MHz).
424 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
425 * or 3.5795 MHz).
624 * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
625 * 12 MHz, or GPIO [21]).
665 #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
726 #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
727 /* (11.981 MHz) */
728 #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
[all …]
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