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/openbmc/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c67 { /* 19.2 MHz */
75 { /* 24 MHz */
76 {25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
78 {25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
83 { /* 25 MHz */
91 { /* 26 MHz */
102 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
103 {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
104 {40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */
105 {500, 12, -1, -1, 10, 8, 4} /* 26 MHz */
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h71 #define R1_CLKSEL_USB (4 << 25)
88 #define R2_CLKSEL_USB (2 << 25)
105 #define RB_CLKSEL_USB (1 << 25)
123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
[all …]
H A Dtimer.c53 * at a rate of 6.144 MHz. Because the device operates on different clocks
86 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
98 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
121 den = 25; in realtime_counter_init()
137 /* Program it for 38.4 MHz */ in realtime_counter_init()
139 den = 25; in realtime_counter_init()
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
49 # 25 chars 20 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
H A Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
H A Dnxp,tja11xx.yaml39 typically derived from an external 25MHz crystal. Alternatively,
40 a 50MHz clock signal generated by an external oscillator can be
41 connected to pin REF_CLK. A third option is to connect a 25MHz
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
66 xtal25mhz: xtal25mhz@25M {
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
[all …]
/openbmc/qemu/include/hw/misc/
H A Daspeed_scu.h103 * 25:23 APB PCLK divider selection
131 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
148 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
150 * The default frequency is 792Mhz when CLKIN = 24MHz
162 * 23 Enable 25 MHz reference clock input
269 * 25 Enable eSPI mode
271 * 23 Select 25 MHz reference clock input mode
301 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25)
338 * 25 Enable H-PLL reset
345 * (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1)
[all …]
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
132 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/
H A Dtypes.h21 #define SC_10MHZ 10000000U /* 10MHz */
22 #define SC_20MHZ 20000000U /* 20MHz */
23 #define SC_25MHZ 25000000U /* 25MHz */
24 #define SC_27MHZ 27000000U /* 27MHz */
25 #define SC_40MHZ 40000000U /* 40MHz */
26 #define SC_45MHZ 45000000U /* 45MHz */
27 #define SC_50MHZ 50000000U /* 50MHz */
28 #define SC_60MHZ 60000000U /* 60MHz */
29 #define SC_66MHZ 66666666U /* 66MHz */
30 #define SC_74MHZ 74250000U /* 74.25MHz */
[all …]
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c107 #define SPEAR1340_DMA_CLK_ENB 25
164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dqt1010.c77 { QT1010_RD, 0x23, 0xff }, /* 25 c read */ in qt1010_set_params()
102 #define FREQ1 32000000 /* 32 MHz */ in qt1010_set_params()
103 #define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */ in qt1010_set_params()
117 if (freq < 290000000) reg05 = 0x14; /* 290 MHz */ in qt1010_set_params()
118 else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */ in qt1010_set_params()
119 else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */ in qt1010_set_params()
125 /* 07 - set frequency: 32 MHz scale */ in qt1010_set_params()
128 /* 09 - changes every 8/24 MHz */ in qt1010_set_params()
132 /* 0a - set frequency: 4 MHz scale (max 28 MHz) */ in qt1010_set_params()
133 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ in qt1010_set_params()
[all …]
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
52 25 40 ? chip initialization
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_consts.h23 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
26 823437500, /* 823.4375 MHz PLL */
33 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
36 783360000, /* 783.36 MHz */
43 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
46 796875000, /* 796.875 MHz */
53 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
56 816000000, /* 816 MHz */
63 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
66 830078125, /* 830.78125 MHz */
[all …]
/openbmc/linux/drivers/clk/mvebu/
H A Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
169 { "tdm", NULL, 25 },
H A Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
115 return 25 * 1000 * 1000; in armada_39x_refclk_ratio()
/openbmc/u-boot/board/ti/am43xx/
H A Dboard.c57 { /* 19.2 MHz */
65 { /* 24 MHz */
73 { /* 25 MHz */
81 { /* 26 MHz */
82 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
84 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
85 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
86 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
87 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
92 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
[all …]
/openbmc/u-boot/board/armadeus/apf27/
H A Dapf27.h27 * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
29 #define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
33 #define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
36 #define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */
38 #define CONFIG_SPLL_FREQ 300 /* MHz */
41 #define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
46 #define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */
47 #define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */
48 #define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */
49 #define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-pro4.c23 /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ in vpll_init()
56 /* Set VPLA_K and VPLB_K for AXO: 25MHz */ in vpll_init()
66 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ in vpll_init()
H A Dpll-ld4.c31 /* AXO: 25MHz */ in upll_init()
35 /* AXO: default 24.576MHz */ in upll_init()
98 /* AXO: 25MHz */ in vpll_init()
108 /* AXO: default 24.576MHz */ in vpll_init()
/openbmc/linux/drivers/clk/versatile/
H A Dclk-icst.c108 * 33 or 25 MHz respectively. in vco_get()
263 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_round_rate()
268 /* Slam to closest 0.25 MHz */ in icst_round_rate()
274 * If we're below or less than halfway from 25 to 33 MHz in icst_round_rate()
275 * select 25 MHz in icst_round_rate()
439 /* Minimum 12 MHz, VDW = 4 */
442 * Maximum 160 MHz, VDW = 152 for all core modules, but
444 * go to 200 MHz (max VDW = 192).
457 /* Minimum 3 MHz, VDW = 4 */
459 /* Maximum 50 MHz, VDW = 192 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
/openbmc/u-boot/doc/
H A DREADME.m54418twr119 make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock
120 make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock
121 make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
122 …make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input c…
123 make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock
124 make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock
135 CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
136 INP CLK 50 MHz VCO CLK 500 MHz
182 cpufreq = 250 MHz
183 busfreq = 125 MHz
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