1d9cc193cSOleksij Rempel# SPDX-License-Identifier: GPL-2.0+ 2d9cc193cSOleksij Rempel%YAML 1.2 3d9cc193cSOleksij Rempel--- 4d9cc193cSOleksij Rempel$id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml# 5d9cc193cSOleksij Rempel$schema: http://devicetree.org/meta-schemas/core.yaml# 6d9cc193cSOleksij Rempel 7d9cc193cSOleksij Rempeltitle: NXP TJA11xx PHY 8d9cc193cSOleksij Rempel 9d9cc193cSOleksij Rempelmaintainers: 10d9cc193cSOleksij Rempel - Andrew Lunn <andrew@lunn.ch> 11d9cc193cSOleksij Rempel - Florian Fainelli <f.fainelli@gmail.com> 12d9cc193cSOleksij Rempel - Heiner Kallweit <hkallweit1@gmail.com> 13d9cc193cSOleksij Rempel 14d9cc193cSOleksij Rempeldescription: 15d9cc193cSOleksij Rempel Bindings for NXP TJA11xx automotive PHYs 16d9cc193cSOleksij Rempel 17d9cc193cSOleksij RempelallOf: 18d9cc193cSOleksij Rempel - $ref: ethernet-phy.yaml# 19d9cc193cSOleksij Rempel 20d9cc193cSOleksij RempelpatternProperties: 21d9cc193cSOleksij Rempel "^ethernet-phy@[0-9a-f]+$": 22d9cc193cSOleksij Rempel type: object 23d9cc193cSOleksij Rempel description: | 24d9cc193cSOleksij Rempel Some packages have multiple PHYs. Secondary PHY should be defines as 25d9cc193cSOleksij Rempel subnode of the first (parent) PHY. 26d9cc193cSOleksij Rempel 27d9cc193cSOleksij Rempel properties: 28d9cc193cSOleksij Rempel reg: 29d9cc193cSOleksij Rempel minimum: 0 30d9cc193cSOleksij Rempel maximum: 31 31d9cc193cSOleksij Rempel description: 32d9cc193cSOleksij Rempel The ID number for the child PHY. Should be +1 of parent PHY. 33d9cc193cSOleksij Rempel 34*52b2fe45SWei Fang nxp,rmii-refclk-in: 35*52b2fe45SWei Fang type: boolean 36*52b2fe45SWei Fang description: | 37*52b2fe45SWei Fang The REF_CLK is provided for both transmitted and received data 38*52b2fe45SWei Fang in RMII mode. This clock signal is provided by the PHY and is 39*52b2fe45SWei Fang typically derived from an external 25MHz crystal. Alternatively, 40*52b2fe45SWei Fang a 50MHz clock signal generated by an external oscillator can be 41*52b2fe45SWei Fang connected to pin REF_CLK. A third option is to connect a 25MHz 42*52b2fe45SWei Fang clock to pin CLK_IN_OUT. So, the REF_CLK should be configured 43*52b2fe45SWei Fang as input or output according to the actual circuit connection. 44*52b2fe45SWei Fang If present, indicates that the REF_CLK will be configured as 45*52b2fe45SWei Fang interface reference clock input when RMII mode enabled. 46*52b2fe45SWei Fang If not present, the REF_CLK will be configured as interface 47*52b2fe45SWei Fang reference clock output when RMII mode enabled. 48*52b2fe45SWei Fang Only supported on TJA1100 and TJA1101. 49*52b2fe45SWei Fang 50d9cc193cSOleksij Rempel required: 51d9cc193cSOleksij Rempel - reg 52d9cc193cSOleksij Rempel 536fdc6e23SRob HerringunevaluatedProperties: false 546fdc6e23SRob Herring 55d9cc193cSOleksij Rempelexamples: 56d9cc193cSOleksij Rempel - | 57d9cc193cSOleksij Rempel mdio { 58d9cc193cSOleksij Rempel #address-cells = <1>; 59d9cc193cSOleksij Rempel #size-cells = <0>; 60d9cc193cSOleksij Rempel 61d9cc193cSOleksij Rempel tja1101_phy0: ethernet-phy@4 { 62d9cc193cSOleksij Rempel reg = <0x4>; 63*52b2fe45SWei Fang nxp,rmii-refclk-in; 64d9cc193cSOleksij Rempel }; 65d9cc193cSOleksij Rempel }; 66d9cc193cSOleksij Rempel - | 67d9cc193cSOleksij Rempel mdio { 68d9cc193cSOleksij Rempel #address-cells = <1>; 69d9cc193cSOleksij Rempel #size-cells = <0>; 70d9cc193cSOleksij Rempel 71d9cc193cSOleksij Rempel tja1102_phy0: ethernet-phy@4 { 72d9cc193cSOleksij Rempel reg = <0x4>; 73d9cc193cSOleksij Rempel #address-cells = <1>; 74d9cc193cSOleksij Rempel #size-cells = <0>; 75d9cc193cSOleksij Rempel 76d9cc193cSOleksij Rempel tja1102_phy1: ethernet-phy@5 { 77d9cc193cSOleksij Rempel reg = <0x5>; 78d9cc193cSOleksij Rempel }; 79d9cc193cSOleksij Rempel }; 80d9cc193cSOleksij Rempel }; 81