Lines Matching +full:25 +full:mhz

103  *  25:23  APB PCLK divider selection
131  *  (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
148  *  (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
150  * The default frequency is 792Mhz when CLKIN = 24MHz
162  * 23     Enable 25 MHz reference clock input
269  * 25     Enable eSPI mode
271  * 23     Select 25 MHz reference clock input mode
301 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE           (0x1 << 25)
338  *  25     Enable H-PLL reset
345  *  (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1)
347  * The default frequency is 1200Mhz when CLKIN = 25MHz
362  *  22:20  RGMII 125MHz clock divider ration
363  *  19:16  RGMII 50MHz clock divider ration
383  *  27:25  RGMIICLK_DIV