Lines Matching +full:25 +full:mhz

27  * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
29 #define ACFG_MPCTL0_VAL		0x01EF15D5	/* 399.000 MHz */
33 #define ACFG_CLK_FREQ	(CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
36 #define ACFG_SPCTL0_VAL		0x0475206F	/* 299.99937 MHz */
38 #define CONFIG_SPLL_FREQ	300		/* MHz */
41 #define CONFIG_ARM_FREQ		399	/* up to 400 MHz */
46 #define CONFIG_PERIF1_FREQ	16	/* 16.625 MHz UART, GPT, PWM */
47 #define CONFIG_PERIF2_FREQ	33	/* 33.25 MHz CSPI and SDHC */
48 #define CONFIG_PERIF3_FREQ	33	/* 33.25 MHz LCD */
49 #define CONFIG_PERIF4_FREQ	33	/* 33.25 MHz CSI */
50 #define CONFIG_SSI1_FREQ	66	/* 66.50 MHz SSI1 */
51 #define CONFIG_SSI2_FREQ	66	/* 66.50 MHz SSI2 */
52 #define CONFIG_MSHC_FREQ	66	/* 66.50 MHz MSHC */
53 #define CONFIG_H264_FREQ	66	/* 66.50 MHz H264 */
58 #define CONFIG_NFC_FREQ		44	/* NFC Clock up to 44 MHz wh 133MHz */
61 #define CONFIG_USB_FREQ		60	/* 60 MHz */
77 #define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
123 #define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
169 #define ACFG_SDRAM_EXIT_PWD		25 /* ns exit power
397 /* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/
413 	|(((CONFIG_CLK0_EN)&0x01)<<25)\