Home
last modified time | relevance | path

Searched +full:24 +full:gbit (Results 1 – 25 of 43) sorted by relevance

12

/openbmc/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Diavf.rst126 # ip link add link eth0 eth0.24 type vlan proto 802.1ad id 24
127 # ip link add link eth0.24 eth0.24.371 type vlan proto 802.1Q id 371
129 Where "24" and "371" are example VLAN IDs.
159 to 1Gbit for tc0 and 3Gbit for tc1.
164 queues 16@0 16@16 hw 1 mode channel shaper bw_rlimit min_rate 1Gbit 2Gbit
165 max_rate 1Gbit 3Gbit
181 For example: min_rate 1Gbit 3Gbit: Verify bandwidth limit using network
H A Di40e.rst242 | 31 28 24 20 16 | 15 12 8 4 0 |
479 ip link add link eth0 eth0.24 type vlan proto 802.1ad id 24
480 ip link add link eth0.24 eth0.24.371 type vlan proto 802.1Q id 371
482 Where "24" and "371" are example VLAN IDs.
668 to 1Gbit for tc0 and 3Gbit for tc1.
673 queues 16@0 16@16 hw 1 mode channel shaper bw_rlimit min_rate 1Gbit 2Gbit
674 max_rate 1Gbit 3Gbit
690 For example: min_rate 1Gbit 3Gbit: Verify bandwidth limit using network
/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2.c643 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | in hw_atl2_hw_multicast_list_set()
703 {0xfU, 0xffU}, /* 10Gbit */ in hw_atl2_hw_interrupt_moderation_set()
704 {0xfU, 0x1ffU}, /* 5Gbit */ in hw_atl2_hw_interrupt_moderation_set()
705 {0xfU, 0x1ffU}, /* 5Gbit 5GS */ in hw_atl2_hw_interrupt_moderation_set()
706 {0xfU, 0x1ffU}, /* 2.5Gbit */ in hw_atl2_hw_interrupt_moderation_set()
707 {0xfU, 0x1ffU}, /* 1Gbit */ in hw_atl2_hw_interrupt_moderation_set()
711 {0x6U, 0x38U},/* 10Gbit */ in hw_atl2_hw_interrupt_moderation_set()
712 {0xCU, 0x70U},/* 5Gbit */ in hw_atl2_hw_interrupt_moderation_set()
713 {0xCU, 0x70U},/* 5Gbit 5GS */ in hw_atl2_hw_interrupt_moderation_set()
714 {0x18U, 0xE0U},/* 2.5Gbit */ in hw_atl2_hw_interrupt_moderation_set()
[all …]
/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_b0.c547 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | in hw_atl_b0_hw_mac_addr_set()
593 * Value 24 in 256byte units in hw_atl_b0_hw_init()
595 aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24); in hw_atl_b0_hw_init()
689 (buff->len_l2 << 24); in hw_atl_b0_hw_ring_tx_xmit()
1088 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | in hw_atl_b0_hw_multicast_list_set()
1143 {0xfU, 0xffU}, /* 10Gbit */ in hw_atl_b0_hw_interrupt_moderation_set()
1144 {0xfU, 0x1ffU}, /* 5Gbit */ in hw_atl_b0_hw_interrupt_moderation_set()
1145 {0xfU, 0x1ffU}, /* 5Gbit 5GS */ in hw_atl_b0_hw_interrupt_moderation_set()
1146 {0xfU, 0x1ffU}, /* 2.5Gbit */ in hw_atl_b0_hw_interrupt_moderation_set()
1147 {0xfU, 0x1ffU}, /* 1Gbit */ in hw_atl_b0_hw_interrupt_moderation_set()
[all …]
H A Dhw_atl_a0.c337 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | in hw_atl_a0_hw_mac_addr_set()
462 (buff->len_l2 << 24) | in hw_atl_a0_hw_ring_tx_xmit()
795 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | in hw_atl_a0_hw_multicast_list_set()
838 0x01CU, /* 10Gbit */ in hw_atl_a0_hw_interrupt_moderation_set()
839 0x039U, /* 5Gbit */ in hw_atl_a0_hw_interrupt_moderation_set()
840 0x039U, /* 5Gbit 5GS */ in hw_atl_a0_hw_interrupt_moderation_set()
841 0x073U, /* 2.5Gbit */ in hw_atl_a0_hw_interrupt_moderation_set()
842 0x120U, /* 1Gbit */ in hw_atl_a0_hw_interrupt_moderation_set()
/openbmc/u-boot/board/freescale/ls1012afrdm/
H A DREADME15 - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
40 - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S49 * EC1. Modify DDR2 init preliminary size to 1Gbit, and BL=4.
159 cmp r3, r2, lsr #24 @ record max
161 orrgt r1, r1, r3, lsl #24
243 mov r1, r1, lsr #24
257 ldr r0, =0x1e7890a0 @ check LHCR0[27:24]=0x6
259 mov r1, r1, lsr #24
338 ldr r2, =0x033103F1 @ load PLL parameter for 24Mhz CLKIN (396:324)
339 /* ldr r2, =0x019001F0 @ load PLL parameter for 24Mhz CLKIN (408:336) */
342 mov r1, r1, lsr #24
589 bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2
[all …]
/openbmc/u-boot/arch/arm/mach-at91/
H A DKconfig172 24AA02E48. The SAMA5D2 SiP integrates the ARM Cortex-A5
173 processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lsxhl.cfg49 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
62 # bit27-24: 2, 3 cycle tRRD
76 # bit3-2: 3, Cs0size=1Gbit
163 # bit31-24: 0x0f, Size (i.e. 256MB)
184 # bit31-24: 0 required
/openbmc/linux/drivers/net/dsa/microchip/
H A Dksz9477.c480 data = ((addr[2] << 24) | (addr[3] << 16)); in ksz9477_fdb_add()
504 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); in ksz9477_fdb_add()
536 data = ((addr[2] << 24) | (addr[3] << 16)); in ksz9477_fdb_del()
605 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; in ksz9477_convert_alu()
680 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); in ksz9477_mdb_add()
759 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); in ksz9477_mdb_del()
894 bool gbit; in ksz9477_get_interface() local
899 gbit = ksz_get_gbit(dev, port); in ksz9477_get_interface()
901 interface = ksz_get_xmii(dev, port, gbit); in ksz9477_get_interface()
H A Dksz_common.c333 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
341 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
367 [STATIC_MAC_FID] = 24,
372 [DYNAMIC_MAC_SRC_PORT] = 24,
411 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
422 [DYNAMIC_MAC_ENTRIES] = 24,
2843 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) in ksz_get_xmii() argument
2856 if (gbit) in ksz_get_xmii()
2907 bool gbit = false; in ksz_get_gbit() local
2916 gbit = true; in ksz_get_gbit()
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbgmac.c2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
775 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; in bgmac_write_mac_address()
825 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
905 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
988 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset in bgmac_chip_reset()
1044 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1098 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S39 * V2 |2015.04.24 : 1.[P1] Add disabling all DRAM requests during PHY init
47 * V6 |2015.08.24 : 1.[P1] Fix SCU160 parameter value for CLKIN=25MHz condition
62 * V12|2016.06.24 : 1.[P1] Modify LPC Reset input source when eSPI mode enabled
95 * CONFIG_DDR3_8GSTACK // DDR3 8Gbit Stack die
96 * CONFIG_DDR4_4GX8 // DDR4 4Gbit X8 dual part
686 ldr r2, =0xC48066C0 @ load PLL parameter for 24Mhz CLKIN (330)
688 ldr r2, =0x93002400 @ load PLL parameter for 24Mhz CLKIN (396)
690 mov r1, r3, lsr #24 @ Check DDR4
694 ldr r2, =0x930023E0 @ load PLL parameter for 24Mhz CLKIN (384)
696 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (372)
[all …]
/openbmc/u-boot/doc/
H A DREADME.b4860qds55 . Two 10-Gbit Ethernet controllers (10GEC)
56 . Six 1G/2.5-Gbit Ethernet controllers for network communications
82 - 24-bit SPI Flash
/openbmc/linux/Documentation/networking/
H A Ddccp.rst206 > ip route change 10.0.0.0/24 rto_min 250j dev wlan0
212 with very low RTTs (e.g., loopback, Gbit ethernet).
/openbmc/linux/drivers/hwmon/pmbus/
H A Dpmbus_core.c31 #define PMBUS_NAME_SIZE 24
1456 u16 gbit; /* generic status bit */ member
1523 bool upper = !!(attr->gbit & 0xff00); /* need to check STATUS_WORD */ in pmbus_add_sensor_attrs_one()
1548 if (!ret && attr->gbit && in pmbus_add_sensor_attrs_one()
1554 attr->gbit); in pmbus_add_sensor_attrs_one()
1754 .gbit = PB_STATUS_VIN_UV,
1779 .gbit = PB_STATUS_VOUT_OV,
1864 .gbit = PB_STATUS_INPUT,
1875 .gbit = PB_STATUS_IOUT_OC,
1955 .gbit
[all...]
/openbmc/linux/Documentation/admin-guide/nfs/
H A Dnfs-rdma.rst17 The NFS/RDMA client was first included in Linux 2.6.24. The NFS/RDMA server
20 In our testing, we have obtained excellent performance results (full 10Gbit
/openbmc/linux/drivers/scsi/
H A Dscsi_transport_fc.c189 #define FC_VPORTSTATE_MAX_NAMELEN 24
252 { FC_PORTSPEED_1GBIT, "1 Gbit" },
253 { FC_PORTSPEED_2GBIT, "2 Gbit" },
254 { FC_PORTSPEED_4GBIT, "4 Gbit" },
255 { FC_PORTSPEED_10GBIT, "10 Gbit" },
256 { FC_PORTSPEED_8GBIT, "8 Gbit" },
257 { FC_PORTSPEED_16GBIT, "16 Gbit" },
258 { FC_PORTSPEED_32GBIT, "32 Gbit" },
259 { FC_PORTSPEED_20GBIT, "20 Gbit" },
260 { FC_PORTSPEED_40GBIT, "40 Gbit" },
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c165 #define SCHED_RDWR_IDLE_GAP(n) ((n & 0xff) << 24)
261 reg_val |= ((0x1<<24)|(0x1<<30)); in mctl_sys_init()
533 writel((MCTL_DIV2(WR2PRE) << 24) | (MCTL_DIV2(tFAW) << 16) | in mctl_channel_init()
539 writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) | in mctl_channel_init()
548 writel((MCTL_DIV2(tRCD) << 24) | (MCTL_DIV2(tCCD) << 16) | in mctl_channel_init()
551 writel((MCTL_DIV2(tCKSRX) << 24) | (MCTL_DIV2(tCKSRE) << 16) | in mctl_channel_init()
556 /* writel((MCTL_TCKDPDE << 24) | (MCTL_TCKDPX << 16) | in mctl_channel_init()
573 writel((2 << 24) | ((MCTL_DIV2(CL) - 2) << 16) | in mctl_channel_init()
733 setbits_le32(&mctl_phy->dsgcr, 0xf << 24); /* unclear what this is... */ in mctl_channel_init()
885 .tRFC = 260, /* 260ns for 4GBit devices */ in sunxi_dram_init()
[all …]
/openbmc/u-boot/board/vscom/baltos/
H A Dboard.c432 * Note here that we're using CPSW1 since that has a 1Gbit PHY while in board_eth_init()
444 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; in board_eth_init()
/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_post.c219 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
236 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
586 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); in finetuneDQI_L()
705 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in finetuneDQSI()
778 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in cbr_dll2()
1738 /* Check 8Gbit */ in check_dram_size_2500()
1741 reg_14 |= (tRFC >> 24) & 0xFF; in check_dram_size_2500()
1742 /* Check 4Gbit */ in check_dram_size_2500()
1746 /* Check 2Gbit */ in check_dram_size_2500()
1790 /* CLKIN = 24MHz */ in set_mpll_2500()
[all …]
/openbmc/linux/drivers/message/fusion/lsi/
H A Dmpi_cnfg.h236 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1.
306 * 05-24-07 01.05.15 Added Hide Physical Disks with Non-Integrated RAID
802 MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */
1169 U8 MetadataSize; /* 24h */
1228 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24)
1282 U32 Reserved10; /* 24h */
1305 U32 Reserved8; /* 24h */
1327 U32 Reserved7; /* 24h */
1350 U32 Reserved8; /* 24h */
1369 U32 Reserved6; /* 24h */
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c69 #define PRG_ETH0_ADJ_SKEW GENMASK(24, 20)
361 * a register) based on the line-speed (125MHz for Gbit speeds, in meson8b_init_prg_eth()
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training.c108 0x3, /* 1Gbit */
109 0x0, /* 2Gbit */
110 0x4, /* 4Gbit */
111 0x5, /* 8Gbit */
115 0x0 /* TODO: placeholder for 24-Mbit die capacity */
/openbmc/linux/drivers/platform/x86/
H A Dapple-gmux.c387 * eDP mux on retinas, the difference being support for 2.7 versus 5.4 Gbit/s.
849 ver_major = (version >> 24) & 0xff; in gmux_probe()
880 * 2^24 for compatibility with old gmux versions. Cap the max in gmux_probe()

12