183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
26ce89324SYegor Yefremov /*
36ce89324SYegor Yefremov * board.c
46ce89324SYegor Yefremov *
56ce89324SYegor Yefremov * Board functions for TI AM335X based boards
66ce89324SYegor Yefremov *
76ce89324SYegor Yefremov * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
86ce89324SYegor Yefremov */
96ce89324SYegor Yefremov
106ce89324SYegor Yefremov #include <common.h>
116ce89324SYegor Yefremov #include <errno.h>
12b08c8c48SMasahiro Yamada #include <linux/libfdt.h>
136ce89324SYegor Yefremov #include <spl.h>
146ce89324SYegor Yefremov #include <asm/arch/cpu.h>
156ce89324SYegor Yefremov #include <asm/arch/hardware.h>
166ce89324SYegor Yefremov #include <asm/arch/omap.h>
176ce89324SYegor Yefremov #include <asm/arch/ddr_defs.h>
186ce89324SYegor Yefremov #include <asm/arch/clock.h>
196ce89324SYegor Yefremov #include <asm/arch/gpio.h>
206ce89324SYegor Yefremov #include <asm/arch/mmc_host_def.h>
216ce89324SYegor Yefremov #include <asm/arch/sys_proto.h>
226ce89324SYegor Yefremov #include <asm/arch/mem.h>
236ce89324SYegor Yefremov #include <asm/arch/mux.h>
246ce89324SYegor Yefremov #include <asm/io.h>
256ce89324SYegor Yefremov #include <asm/emif.h>
266ce89324SYegor Yefremov #include <asm/gpio.h>
276ce89324SYegor Yefremov #include <i2c.h>
286ce89324SYegor Yefremov #include <miiphy.h>
296ce89324SYegor Yefremov #include <cpsw.h>
306ce89324SYegor Yefremov #include <power/tps65910.h>
316ce89324SYegor Yefremov #include <environment.h>
326ce89324SYegor Yefremov #include <watchdog.h>
336ce89324SYegor Yefremov #include "board.h"
346ce89324SYegor Yefremov
356ce89324SYegor Yefremov DECLARE_GLOBAL_DATA_PTR;
366ce89324SYegor Yefremov
37*67c145a8SYegor Yefremov /* GPIO that controls DIP switch and mPCIe slot */
386ce89324SYegor Yefremov #define DIP_S1 44
39dcf7f6f1SYegor Yefremov #define MPCIE_SW 100
406ce89324SYegor Yefremov
416ce89324SYegor Yefremov static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
426ce89324SYegor Yefremov
baltos_set_console(void)436ce89324SYegor Yefremov static int baltos_set_console(void)
446ce89324SYegor Yefremov {
456ce89324SYegor Yefremov int val, i, dips = 0;
466ce89324SYegor Yefremov char buf[7];
476ce89324SYegor Yefremov
486ce89324SYegor Yefremov for (i = 0; i < 4; i++) {
496ce89324SYegor Yefremov sprintf(buf, "dip_s%d", i + 1);
506ce89324SYegor Yefremov
516ce89324SYegor Yefremov if (gpio_request(DIP_S1 + i, buf)) {
526ce89324SYegor Yefremov printf("failed to export GPIO %d\n", DIP_S1 + i);
536ce89324SYegor Yefremov return 0;
546ce89324SYegor Yefremov }
556ce89324SYegor Yefremov
566ce89324SYegor Yefremov if (gpio_direction_input(DIP_S1 + i)) {
576ce89324SYegor Yefremov printf("failed to set GPIO %d direction\n", DIP_S1 + i);
586ce89324SYegor Yefremov return 0;
596ce89324SYegor Yefremov }
606ce89324SYegor Yefremov
616ce89324SYegor Yefremov val = gpio_get_value(DIP_S1 + i);
626ce89324SYegor Yefremov dips |= val << i;
636ce89324SYegor Yefremov }
646ce89324SYegor Yefremov
656ce89324SYegor Yefremov printf("DIPs: 0x%1x\n", (~dips) & 0xf);
666ce89324SYegor Yefremov
676ce89324SYegor Yefremov if ((dips & 0xf) == 0xe)
68382bee57SSimon Glass env_set("console", "ttyUSB0,115200n8");
696ce89324SYegor Yefremov
706ce89324SYegor Yefremov return 0;
716ce89324SYegor Yefremov }
726ce89324SYegor Yefremov
read_eeprom(BSP_VS_HWPARAM * header)736ce89324SYegor Yefremov static int read_eeprom(BSP_VS_HWPARAM *header)
746ce89324SYegor Yefremov {
756ce89324SYegor Yefremov i2c_set_bus_num(1);
766ce89324SYegor Yefremov
776ce89324SYegor Yefremov /* Check if baseboard eeprom is available */
786ce89324SYegor Yefremov if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
796ce89324SYegor Yefremov puts("Could not probe the EEPROM; something fundamentally "
806ce89324SYegor Yefremov "wrong on the I2C bus.\n");
816ce89324SYegor Yefremov return -ENODEV;
826ce89324SYegor Yefremov }
836ce89324SYegor Yefremov
846ce89324SYegor Yefremov /* read the eeprom using i2c */
856ce89324SYegor Yefremov if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
866ce89324SYegor Yefremov sizeof(BSP_VS_HWPARAM))) {
876ce89324SYegor Yefremov puts("Could not read the EEPROM; something fundamentally"
886ce89324SYegor Yefremov " wrong on the I2C bus.\n");
896ce89324SYegor Yefremov return -EIO;
906ce89324SYegor Yefremov }
916ce89324SYegor Yefremov
926ce89324SYegor Yefremov if (header->Magic != 0xDEADBEEF) {
936ce89324SYegor Yefremov
946ce89324SYegor Yefremov printf("Incorrect magic number (0x%x) in EEPROM\n",
956ce89324SYegor Yefremov header->Magic);
966ce89324SYegor Yefremov
976ce89324SYegor Yefremov /* fill default values */
986ce89324SYegor Yefremov header->SystemId = 211;
996ce89324SYegor Yefremov header->MAC1[0] = 0x00;
1006ce89324SYegor Yefremov header->MAC1[1] = 0x00;
1016ce89324SYegor Yefremov header->MAC1[2] = 0x00;
1026ce89324SYegor Yefremov header->MAC1[3] = 0x00;
1036ce89324SYegor Yefremov header->MAC1[4] = 0x00;
1046ce89324SYegor Yefremov header->MAC1[5] = 0x01;
1056ce89324SYegor Yefremov
1066ce89324SYegor Yefremov header->MAC2[0] = 0x00;
1076ce89324SYegor Yefremov header->MAC2[1] = 0x00;
1086ce89324SYegor Yefremov header->MAC2[2] = 0x00;
1096ce89324SYegor Yefremov header->MAC2[3] = 0x00;
1106ce89324SYegor Yefremov header->MAC2[4] = 0x00;
1116ce89324SYegor Yefremov header->MAC2[5] = 0x02;
1126ce89324SYegor Yefremov
1136ce89324SYegor Yefremov header->MAC3[0] = 0x00;
1146ce89324SYegor Yefremov header->MAC3[1] = 0x00;
1156ce89324SYegor Yefremov header->MAC3[2] = 0x00;
1166ce89324SYegor Yefremov header->MAC3[3] = 0x00;
1176ce89324SYegor Yefremov header->MAC3[4] = 0x00;
1186ce89324SYegor Yefremov header->MAC3[5] = 0x03;
1196ce89324SYegor Yefremov }
1206ce89324SYegor Yefremov
1216ce89324SYegor Yefremov return 0;
1226ce89324SYegor Yefremov }
1236ce89324SYegor Yefremov
1246ce89324SYegor Yefremov #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
1256ce89324SYegor Yefremov
1266ce89324SYegor Yefremov static const struct ddr_data ddr3_baltos_data = {
1276ce89324SYegor Yefremov .datardsratio0 = MT41K256M16HA125E_RD_DQS,
1286ce89324SYegor Yefremov .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
1296ce89324SYegor Yefremov .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
1306ce89324SYegor Yefremov .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
1316ce89324SYegor Yefremov };
1326ce89324SYegor Yefremov
1336ce89324SYegor Yefremov static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
1346ce89324SYegor Yefremov .cmd0csratio = MT41K256M16HA125E_RATIO,
1356ce89324SYegor Yefremov .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
1366ce89324SYegor Yefremov
1376ce89324SYegor Yefremov .cmd1csratio = MT41K256M16HA125E_RATIO,
1386ce89324SYegor Yefremov .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
1396ce89324SYegor Yefremov
1406ce89324SYegor Yefremov .cmd2csratio = MT41K256M16HA125E_RATIO,
1416ce89324SYegor Yefremov .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
1426ce89324SYegor Yefremov };
1436ce89324SYegor Yefremov
1446ce89324SYegor Yefremov static struct emif_regs ddr3_baltos_emif_reg_data = {
1456ce89324SYegor Yefremov .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
1466ce89324SYegor Yefremov .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
1476ce89324SYegor Yefremov .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
1486ce89324SYegor Yefremov .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
1496ce89324SYegor Yefremov .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
1506ce89324SYegor Yefremov .zq_config = MT41K256M16HA125E_ZQ_CFG,
1516ce89324SYegor Yefremov .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
1526ce89324SYegor Yefremov };
1536ce89324SYegor Yefremov
1546ce89324SYegor Yefremov #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)1556ce89324SYegor Yefremov int spl_start_uboot(void)
1566ce89324SYegor Yefremov {
1576ce89324SYegor Yefremov /* break into full u-boot on 'c' */
1586ce89324SYegor Yefremov return (serial_tstc() && serial_getc() == 'c');
1596ce89324SYegor Yefremov }
1606ce89324SYegor Yefremov #endif
1616ce89324SYegor Yefremov
1626ce89324SYegor Yefremov #define OSC (V_OSCK/1000000)
1636ce89324SYegor Yefremov const struct dpll_params dpll_ddr = {
1646ce89324SYegor Yefremov 266, OSC-1, 1, -1, -1, -1, -1};
1656ce89324SYegor Yefremov const struct dpll_params dpll_ddr_evm_sk = {
1666ce89324SYegor Yefremov 303, OSC-1, 1, -1, -1, -1, -1};
1676ce89324SYegor Yefremov const struct dpll_params dpll_ddr_baltos = {
1686ce89324SYegor Yefremov 400, OSC-1, 1, -1, -1, -1, -1};
1696ce89324SYegor Yefremov
am33xx_spl_board_init(void)1706ce89324SYegor Yefremov void am33xx_spl_board_init(void)
1716ce89324SYegor Yefremov {
1726ce89324SYegor Yefremov int mpu_vdd;
1736ce89324SYegor Yefremov int sil_rev;
1746ce89324SYegor Yefremov
1756ce89324SYegor Yefremov /* Get the frequency */
1766ce89324SYegor Yefremov dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
1776ce89324SYegor Yefremov
1786ce89324SYegor Yefremov /*
1796ce89324SYegor Yefremov * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
1806ce89324SYegor Yefremov * MPU frequencies we support we use a CORE voltage of
1816ce89324SYegor Yefremov * 1.1375V. For MPU voltage we need to switch based on
1826ce89324SYegor Yefremov * the frequency we are running at.
1836ce89324SYegor Yefremov */
1846ce89324SYegor Yefremov i2c_set_bus_num(1);
1856ce89324SYegor Yefremov
186e6b1b58bSYegor Yefremov printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
187e6b1b58bSYegor Yefremov
1886ce89324SYegor Yefremov if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
1896ce89324SYegor Yefremov puts("i2c: cannot access TPS65910\n");
1906ce89324SYegor Yefremov return;
1916ce89324SYegor Yefremov }
1926ce89324SYegor Yefremov
1936ce89324SYegor Yefremov /*
1946ce89324SYegor Yefremov * Depending on MPU clock and PG we will need a different
1956ce89324SYegor Yefremov * VDD to drive at that speed.
1966ce89324SYegor Yefremov */
1976ce89324SYegor Yefremov sil_rev = readl(&cdev->deviceid) >> 28;
1986ce89324SYegor Yefremov mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
1996ce89324SYegor Yefremov dpll_mpu_opp100.m);
2006ce89324SYegor Yefremov
2016ce89324SYegor Yefremov /* Tell the TPS65910 to use i2c */
2026ce89324SYegor Yefremov tps65910_set_i2c_control();
2036ce89324SYegor Yefremov
2046ce89324SYegor Yefremov /* First update MPU voltage. */
2056ce89324SYegor Yefremov if (tps65910_voltage_update(MPU, mpu_vdd))
2066ce89324SYegor Yefremov return;
2076ce89324SYegor Yefremov
2086ce89324SYegor Yefremov /* Second, update the CORE voltage. */
2096ce89324SYegor Yefremov if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
2106ce89324SYegor Yefremov return;
2116ce89324SYegor Yefremov
2126ce89324SYegor Yefremov /* Set CORE Frequencies to OPP100 */
2136ce89324SYegor Yefremov do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
2146ce89324SYegor Yefremov
2156ce89324SYegor Yefremov /* Set MPU Frequency to what we detected now that voltages are set */
2166ce89324SYegor Yefremov do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
2176ce89324SYegor Yefremov
2186ce89324SYegor Yefremov writel(0x000010ff, PRM_DEVICE_INST + 4);
2196ce89324SYegor Yefremov }
2206ce89324SYegor Yefremov
get_dpll_ddr_params(void)2216ce89324SYegor Yefremov const struct dpll_params *get_dpll_ddr_params(void)
2226ce89324SYegor Yefremov {
2236ce89324SYegor Yefremov enable_i2c1_pin_mux();
2246ce89324SYegor Yefremov i2c_set_bus_num(1);
2256ce89324SYegor Yefremov
2266ce89324SYegor Yefremov return &dpll_ddr_baltos;
2276ce89324SYegor Yefremov }
2286ce89324SYegor Yefremov
set_uart_mux_conf(void)2296ce89324SYegor Yefremov void set_uart_mux_conf(void)
2306ce89324SYegor Yefremov {
2316ce89324SYegor Yefremov enable_uart0_pin_mux();
2326ce89324SYegor Yefremov }
2336ce89324SYegor Yefremov
set_mux_conf_regs(void)2346ce89324SYegor Yefremov void set_mux_conf_regs(void)
2356ce89324SYegor Yefremov {
2366ce89324SYegor Yefremov enable_board_pin_mux();
2376ce89324SYegor Yefremov }
2386ce89324SYegor Yefremov
2396ce89324SYegor Yefremov const struct ctrl_ioregs ioregs_baltos = {
2406ce89324SYegor Yefremov .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
2416ce89324SYegor Yefremov .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
2426ce89324SYegor Yefremov .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
2436ce89324SYegor Yefremov .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
2446ce89324SYegor Yefremov .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
2456ce89324SYegor Yefremov };
2466ce89324SYegor Yefremov
sdram_init(void)2476ce89324SYegor Yefremov void sdram_init(void)
2486ce89324SYegor Yefremov {
2496ce89324SYegor Yefremov config_ddr(400, &ioregs_baltos,
2506ce89324SYegor Yefremov &ddr3_baltos_data,
2516ce89324SYegor Yefremov &ddr3_baltos_cmd_ctrl_data,
2526ce89324SYegor Yefremov &ddr3_baltos_emif_reg_data, 0);
2536ce89324SYegor Yefremov }
2546ce89324SYegor Yefremov #endif
2556ce89324SYegor Yefremov
2566ce89324SYegor Yefremov /*
2576ce89324SYegor Yefremov * Basic board specific setup. Pinmux has been handled already.
2586ce89324SYegor Yefremov */
board_init(void)2596ce89324SYegor Yefremov int board_init(void)
2606ce89324SYegor Yefremov {
2616ce89324SYegor Yefremov #if defined(CONFIG_HW_WATCHDOG)
2626ce89324SYegor Yefremov hw_watchdog_init();
2636ce89324SYegor Yefremov #endif
2646ce89324SYegor Yefremov
2656ce89324SYegor Yefremov gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
2666ce89324SYegor Yefremov #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
2676ce89324SYegor Yefremov gpmc_init();
2686ce89324SYegor Yefremov #endif
2696ce89324SYegor Yefremov return 0;
2706ce89324SYegor Yefremov }
2716ce89324SYegor Yefremov
ft_board_setup(void * blob,bd_t * bd)2726ce89324SYegor Yefremov int ft_board_setup(void *blob, bd_t *bd)
2736ce89324SYegor Yefremov {
2746ce89324SYegor Yefremov int node, ret;
2756ce89324SYegor Yefremov unsigned char mac_addr[6];
2766ce89324SYegor Yefremov BSP_VS_HWPARAM header;
2776ce89324SYegor Yefremov
2786ce89324SYegor Yefremov /* get production data */
2796ce89324SYegor Yefremov if (read_eeprom(&header))
2806ce89324SYegor Yefremov return 0;
2816ce89324SYegor Yefremov
2826ce89324SYegor Yefremov /* setup MAC1 */
2836ce89324SYegor Yefremov mac_addr[0] = header.MAC1[0];
2846ce89324SYegor Yefremov mac_addr[1] = header.MAC1[1];
2856ce89324SYegor Yefremov mac_addr[2] = header.MAC1[2];
2866ce89324SYegor Yefremov mac_addr[3] = header.MAC1[3];
2876ce89324SYegor Yefremov mac_addr[4] = header.MAC1[4];
2886ce89324SYegor Yefremov mac_addr[5] = header.MAC1[5];
2896ce89324SYegor Yefremov
2906ce89324SYegor Yefremov
2916ce89324SYegor Yefremov node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
2926ce89324SYegor Yefremov if (node < 0) {
2936ce89324SYegor Yefremov printf("no /soc/fman/ethernet path offset\n");
2946ce89324SYegor Yefremov return -ENODEV;
2956ce89324SYegor Yefremov }
2966ce89324SYegor Yefremov
2976ce89324SYegor Yefremov ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
2986ce89324SYegor Yefremov if (ret) {
2996ce89324SYegor Yefremov printf("error setting local-mac-address property\n");
3006ce89324SYegor Yefremov return -ENODEV;
3016ce89324SYegor Yefremov }
3026ce89324SYegor Yefremov
3036ce89324SYegor Yefremov /* setup MAC2 */
3046ce89324SYegor Yefremov mac_addr[0] = header.MAC2[0];
3056ce89324SYegor Yefremov mac_addr[1] = header.MAC2[1];
3066ce89324SYegor Yefremov mac_addr[2] = header.MAC2[2];
3076ce89324SYegor Yefremov mac_addr[3] = header.MAC2[3];
3086ce89324SYegor Yefremov mac_addr[4] = header.MAC2[4];
3096ce89324SYegor Yefremov mac_addr[5] = header.MAC2[5];
3106ce89324SYegor Yefremov
3116ce89324SYegor Yefremov node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
3126ce89324SYegor Yefremov if (node < 0) {
3136ce89324SYegor Yefremov printf("no /soc/fman/ethernet path offset\n");
3146ce89324SYegor Yefremov return -ENODEV;
3156ce89324SYegor Yefremov }
3166ce89324SYegor Yefremov
3176ce89324SYegor Yefremov ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
3186ce89324SYegor Yefremov if (ret) {
3196ce89324SYegor Yefremov printf("error setting local-mac-address property\n");
3206ce89324SYegor Yefremov return -ENODEV;
3216ce89324SYegor Yefremov }
3226ce89324SYegor Yefremov
3236ce89324SYegor Yefremov printf("\nFDT was successfully setup\n");
3246ce89324SYegor Yefremov
3256ce89324SYegor Yefremov return 0;
3266ce89324SYegor Yefremov }
3276ce89324SYegor Yefremov
328dcf7f6f1SYegor Yefremov static struct module_pin_mux pcie_sw_pin_mux[] = {
329dcf7f6f1SYegor Yefremov {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
330dcf7f6f1SYegor Yefremov {-1},
331dcf7f6f1SYegor Yefremov };
332dcf7f6f1SYegor Yefremov
3336ce89324SYegor Yefremov static struct module_pin_mux dip_pin_mux[] = {
3346ce89324SYegor Yefremov {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
3356ce89324SYegor Yefremov {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
3366ce89324SYegor Yefremov {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
3376ce89324SYegor Yefremov {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
3386ce89324SYegor Yefremov {-1},
3396ce89324SYegor Yefremov };
3406ce89324SYegor Yefremov
3416ce89324SYegor Yefremov #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)3426ce89324SYegor Yefremov int board_late_init(void)
3436ce89324SYegor Yefremov {
3446ce89324SYegor Yefremov #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
3456ce89324SYegor Yefremov BSP_VS_HWPARAM header;
3466ce89324SYegor Yefremov char model[4];
3476ce89324SYegor Yefremov
3486ce89324SYegor Yefremov /* get production data */
3496ce89324SYegor Yefremov if (read_eeprom(&header)) {
350192bc694SBen Whitten strcpy(model, "211");
3516ce89324SYegor Yefremov } else {
3526ce89324SYegor Yefremov sprintf(model, "%d", header.SystemId);
3536ce89324SYegor Yefremov if (header.SystemId == 215) {
3546ce89324SYegor Yefremov configure_module_pin_mux(dip_pin_mux);
3556ce89324SYegor Yefremov baltos_set_console();
3566ce89324SYegor Yefremov }
3576ce89324SYegor Yefremov }
358dcf7f6f1SYegor Yefremov
359dcf7f6f1SYegor Yefremov /* turn power for the mPCIe slot */
360dcf7f6f1SYegor Yefremov configure_module_pin_mux(pcie_sw_pin_mux);
361dcf7f6f1SYegor Yefremov if (gpio_request(MPCIE_SW, "mpcie_sw")) {
362dcf7f6f1SYegor Yefremov printf("failed to export GPIO %d\n", MPCIE_SW);
363dcf7f6f1SYegor Yefremov return -ENODEV;
364dcf7f6f1SYegor Yefremov }
365dcf7f6f1SYegor Yefremov if (gpio_direction_output(MPCIE_SW, 1)) {
366dcf7f6f1SYegor Yefremov printf("failed to set GPIO %d direction\n", MPCIE_SW);
367dcf7f6f1SYegor Yefremov return -ENODEV;
368dcf7f6f1SYegor Yefremov }
369dcf7f6f1SYegor Yefremov
370382bee57SSimon Glass env_set("board_name", model);
3716ce89324SYegor Yefremov #endif
3726ce89324SYegor Yefremov
3736ce89324SYegor Yefremov return 0;
3746ce89324SYegor Yefremov }
3756ce89324SYegor Yefremov #endif
3766ce89324SYegor Yefremov
3776ce89324SYegor Yefremov #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
3786ce89324SYegor Yefremov (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
cpsw_control(int enabled)3796ce89324SYegor Yefremov static void cpsw_control(int enabled)
3806ce89324SYegor Yefremov {
3816ce89324SYegor Yefremov /* VTP can be added here */
3826ce89324SYegor Yefremov
3836ce89324SYegor Yefremov return;
3846ce89324SYegor Yefremov }
3856ce89324SYegor Yefremov
3866ce89324SYegor Yefremov static struct cpsw_slave_data cpsw_slaves[] = {
3876ce89324SYegor Yefremov {
3886ce89324SYegor Yefremov .slave_reg_ofs = 0x208,
3896ce89324SYegor Yefremov .sliver_reg_ofs = 0xd80,
3906ce89324SYegor Yefremov .phy_addr = 0,
3916ce89324SYegor Yefremov },
3926ce89324SYegor Yefremov {
3936ce89324SYegor Yefremov .slave_reg_ofs = 0x308,
3946ce89324SYegor Yefremov .sliver_reg_ofs = 0xdc0,
3956ce89324SYegor Yefremov .phy_addr = 7,
3966ce89324SYegor Yefremov },
3976ce89324SYegor Yefremov };
3986ce89324SYegor Yefremov
3996ce89324SYegor Yefremov static struct cpsw_platform_data cpsw_data = {
4006ce89324SYegor Yefremov .mdio_base = CPSW_MDIO_BASE,
4016ce89324SYegor Yefremov .cpsw_base = CPSW_BASE,
4026ce89324SYegor Yefremov .mdio_div = 0xff,
4036ce89324SYegor Yefremov .channels = 8,
4046ce89324SYegor Yefremov .cpdma_reg_ofs = 0x800,
4056ce89324SYegor Yefremov .slaves = 2,
4066ce89324SYegor Yefremov .slave_data = cpsw_slaves,
4076ce89324SYegor Yefremov .active_slave = 1,
4086ce89324SYegor Yefremov .ale_reg_ofs = 0xd00,
4096ce89324SYegor Yefremov .ale_entries = 1024,
4106ce89324SYegor Yefremov .host_port_reg_ofs = 0x108,
4116ce89324SYegor Yefremov .hw_stats_reg_ofs = 0x900,
4126ce89324SYegor Yefremov .bd_ram_ofs = 0x2000,
4136ce89324SYegor Yefremov .mac_control = (1 << 5),
4146ce89324SYegor Yefremov .control = cpsw_control,
4156ce89324SYegor Yefremov .host_port_num = 0,
4166ce89324SYegor Yefremov .version = CPSW_CTRL_VERSION_2,
4176ce89324SYegor Yefremov };
4186ce89324SYegor Yefremov #endif
4196ce89324SYegor Yefremov
420b432b1ebSFaiz Abbas #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
4216ce89324SYegor Yefremov && defined(CONFIG_SPL_BUILD)) || \
4226ce89324SYegor Yefremov ((defined(CONFIG_DRIVER_TI_CPSW) || \
42395de1e2fSPaul Kocialkowski defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
4246ce89324SYegor Yefremov !defined(CONFIG_SPL_BUILD))
board_eth_init(bd_t * bis)4256ce89324SYegor Yefremov int board_eth_init(bd_t *bis)
4266ce89324SYegor Yefremov {
4276ce89324SYegor Yefremov int rv, n = 0;
4286ce89324SYegor Yefremov uint8_t mac_addr[6];
4296ce89324SYegor Yefremov uint32_t mac_hi, mac_lo;
4306ce89324SYegor Yefremov
4316ce89324SYegor Yefremov /*
4326ce89324SYegor Yefremov * Note here that we're using CPSW1 since that has a 1Gbit PHY while
4336ce89324SYegor Yefremov * CSPW0 has a 100Mbit PHY.
4346ce89324SYegor Yefremov *
4356ce89324SYegor Yefremov * On product, CPSW1 maps to port labeled WAN.
4366ce89324SYegor Yefremov */
4376ce89324SYegor Yefremov
4386ce89324SYegor Yefremov /* try reading mac address from efuse */
4396ce89324SYegor Yefremov mac_lo = readl(&cdev->macid1l);
4406ce89324SYegor Yefremov mac_hi = readl(&cdev->macid1h);
4416ce89324SYegor Yefremov mac_addr[0] = mac_hi & 0xFF;
4426ce89324SYegor Yefremov mac_addr[1] = (mac_hi & 0xFF00) >> 8;
4436ce89324SYegor Yefremov mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
4446ce89324SYegor Yefremov mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
4456ce89324SYegor Yefremov mac_addr[4] = mac_lo & 0xFF;
4466ce89324SYegor Yefremov mac_addr[5] = (mac_lo & 0xFF00) >> 8;
4476ce89324SYegor Yefremov
4486ce89324SYegor Yefremov #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
4496ce89324SYegor Yefremov (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
45000caae6dSSimon Glass if (!env_get("ethaddr")) {
4516ce89324SYegor Yefremov printf("<ethaddr> not set. Validating first E-fuse MAC\n");
4526ce89324SYegor Yefremov
4536ce89324SYegor Yefremov if (is_valid_ethaddr(mac_addr))
454fd1e959eSSimon Glass eth_env_set_enetaddr("ethaddr", mac_addr);
4556ce89324SYegor Yefremov }
4566ce89324SYegor Yefremov
4576ce89324SYegor Yefremov #ifdef CONFIG_DRIVER_TI_CPSW
4586ce89324SYegor Yefremov writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
4596ce89324SYegor Yefremov cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
4606ce89324SYegor Yefremov rv = cpsw_register(&cpsw_data);
4616ce89324SYegor Yefremov if (rv < 0)
4626ce89324SYegor Yefremov printf("Error %d registering CPSW switch\n", rv);
4636ce89324SYegor Yefremov else
4646ce89324SYegor Yefremov n += rv;
4656ce89324SYegor Yefremov #endif
4666ce89324SYegor Yefremov
4676ce89324SYegor Yefremov /*
4686ce89324SYegor Yefremov *
4696ce89324SYegor Yefremov * CPSW RGMII Internal Delay Mode is not supported in all PVT
4706ce89324SYegor Yefremov * operating points. So we must set the TX clock delay feature
4716ce89324SYegor Yefremov * in the AR8051 PHY. Since we only support a single ethernet
4726ce89324SYegor Yefremov * device in U-Boot, we only do this for the first instance.
4736ce89324SYegor Yefremov */
4746ce89324SYegor Yefremov #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
4756ce89324SYegor Yefremov #define AR8051_PHY_DEBUG_DATA_REG 0x1e
4766ce89324SYegor Yefremov #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
4776ce89324SYegor Yefremov #define AR8051_RGMII_TX_CLK_DLY 0x100
4786ce89324SYegor Yefremov const char *devname;
4796ce89324SYegor Yefremov devname = miiphy_get_current_dev();
4806ce89324SYegor Yefremov
4816ce89324SYegor Yefremov miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
4826ce89324SYegor Yefremov AR8051_DEBUG_RGMII_CLK_DLY_REG);
4836ce89324SYegor Yefremov miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
4846ce89324SYegor Yefremov AR8051_RGMII_TX_CLK_DLY);
4856ce89324SYegor Yefremov #endif
4866ce89324SYegor Yefremov return n;
4876ce89324SYegor Yefremov }
4886ce89324SYegor Yefremov #endif
489