Lines Matching +full:24 +full:gbit
49 * EC1. Modify DDR2 init preliminary size to 1Gbit, and BL=4.
159 cmp r3, r2, lsr #24 @ record max
161 orrgt r1, r1, r3, lsl #24
243 mov r1, r1, lsr #24
257 ldr r0, =0x1e7890a0 @ check LHCR0[27:24]=0x6
259 mov r1, r1, lsr #24
338 ldr r2, =0x033103F1 @ load PLL parameter for 24Mhz CLKIN (396:324)
339 /* ldr r2, =0x019001F0 @ load PLL parameter for 24Mhz CLKIN (408:336) */
342 mov r1, r1, lsr #24
589 bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2
590 mov r2, r1, lsr #24
603 tRFC = 110ns/1Gbit, 160ns/2Gbit, 300ns/4Gbit
623 ldr r1, =0x00000531 @ Default set to 1Gbit
792 tRFC = 105ns/512Mbit, 127.5ns/1Gbit, 197.5ns/2Gbit, 327.5ns/4Gbit
812 ldr r1, =0x00000521 @ Default set to 1Gbit
1076 orr r1, r1, r2, lsl #24
1232 mov r1, r2, lsr #24
1235 orr r2, r2, r1, lsl #24
2487 bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2
2488 mov r2, r1, lsr #24
2496 str r1, [r0] @ set to 4Gbit
2508 str r1, [r0] @ set to 4Gbit
2525 orr r5, r5, #0x20 @ >= 1Gbit
2541 cmp r2, r1 @ == 4Gbit
2548 cmp r2, r1 @ == 2Gbit
2552 orr r5, r5, #0x01 @ == 1Gbit
2614 mov r2, r1, lsr #24
2803 mov r1, r1, lsr #24
3034 mov r1, r1, lsr #24