Lines Matching +full:24 +full:gbit

165 #define SCHED_RDWR_IDLE_GAP(n)            ((n & 0xff) << 24)
261 		reg_val |= ((0x1<<24)|(0x1<<30));  in mctl_sys_init()
533 	writel((MCTL_DIV2(WR2PRE) << 24) | (MCTL_DIV2(tFAW) << 16) |  in mctl_channel_init()
539 	writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) |  in mctl_channel_init()
548 	writel((MCTL_DIV2(tRCD) << 24) | (MCTL_DIV2(tCCD) << 16) |  in mctl_channel_init()
551 	writel((MCTL_DIV2(tCKSRX) << 24) | (MCTL_DIV2(tCKSRE) << 16) |  in mctl_channel_init()
556 	/* writel((MCTL_TCKDPDE << 24) | (MCTL_TCKDPX << 16) |  in mctl_channel_init()
573 		writel((2 << 24) | ((MCTL_DIV2(CL) - 2) << 16) |  in mctl_channel_init()
733 	setbits_le32(&mctl_phy->dsgcr, 0xf << 24); /* unclear what this is... */  in mctl_channel_init()
885 		.tRFC  = 260,	/* 260ns for 4GBit devices */  in sunxi_dram_init()
886 				/* 350ns @ 8GBit */  in sunxi_dram_init()