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/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
10 * information contained in the core-isa.h header file.
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
25 /* Copyright (c) 1999-2020 Tensilica Inc.
49 /*----------------------------------------------------------------------
51 ----------------------------------------------------------------------*/
55 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
117 #define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */
118 #define XCHAL_CA_WRITEBACK 7 /* cache enabled (write-back) mode */
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/openbmc/linux/arch/nios2/mm/
H A Dtlb.c22 ((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
38 return ((addr | 0xC0000000UL) >> PAGE_SHIFT) << 2; in pteaddr_invalid()
47 unsigned int way; in replace_tlb_one_pid() local
50 /* remember pid/way until we return. */ in replace_tlb_one_pid()
53 WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2); in replace_tlb_one_pid()
55 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in replace_tlb_one_pid()
60 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
64 if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT)) in replace_tlb_one_pid()
73 (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
90 pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr); in flush_tlb_one_pid()
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/openbmc/linux/arch/x86/kernel/cpu/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
31 #define LVL_1_DATA 2
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
63 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
65 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
66 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
67 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
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H A Dintel.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <asm/intel-family.h>
67 * Processors which have self-snooping capability can handle conflicting
75 switch (c->x86_vfm) { in check_memory_type_self_snoop_errata()
107 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
109 switch (c->x86_vfm) { in probe_xeon_phi_r3mwait()
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
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/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S1 /* SPDX-License-Identifier: GPL-2.0+ */
19 * Flush the whole D-cache.
21 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
23 * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
29 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
37 cmp r1, #2 @ see what cache we have at this level
38 blt skip @ skip if no cache, or just i-cache
39 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
45 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
46 clz r5, r4 @ find bit position of way size increment
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/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
10 * information contained in the core-isa.h header file.
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
25 /* Copyright (c) 1999-2010 Tensilica Inc.
49 /*----------------------------------------------------------------------
51 ----------------------------------------------------------------------*/
54 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
111 #define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
112 #define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
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/openbmc/u-boot/arch/powerpc/include/asm/
H A De300.h15 * Hardware Implementation-Dependent Register 0 (HID0)
77 * Hardware Implementation-Dependent Register 2 (HID2)
84 #define HID2_IWLCK_001 0x00002000 /* way 0 locked */
85 #define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
86 #define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
87 #define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
88 #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
89 #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
28 compatible = "arm,armv7-timer";
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H A Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
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/openbmc/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
29 #define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)
43 #define SPR_CPUCFGR (SPRGROUP_SYS + 2)
71 #define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
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/openbmc/linux/scripts/tracing/
H A Dftrace-bisect.sh2 # SPDX-License-Identifier: GPL-2.0
25 # The old (slow) way, for kernels before v5.1.
27 # [old-way] # cat available_filter_functions > ~/full-file
29 # [old-way] *** Note *** this process will take several minutes to update the
30 # [old-way] filters. Setting multiple functions is an O(n^2) operation, and we
31 # [old-way] are dealing with thousands of functions. So go have coffee, talk
32 # [old-way] with your coworkers, read facebook. And eventually, this operation
33 # [old-way] will end.
35 # The new way (using numbers) is an O(n) operation, and usually takes less than a second.
37 # seq `wc -l available_filter_functions | cut -d' ' -f1` > ~/full-file
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/openbmc/linux/arch/mips/kernel/
H A Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
64 #define CP0_DCACHE_TAG_LO $28, 2
68 #define CP0_DCACHE_TAG_HI $29, 2
84 #define BRCM_ZSC_REQ_BUFFER_REG 2 << 3
107 .align 2
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
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/openbmc/linux/arch/arm/mm/
H A Dcache-xsc3l2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
51 __asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way)); in xsc3_l2_inv_all()
61 if (va != -1) in l2_unmap_va()
70 unsigned long pa_offset = pa << (32 - PAGE_SHIFT); in l2_map_va()
71 if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { in l2_map_va()
80 return va + (pa_offset >> (32 - PAGE_SHIFT)); in l2_map_va()
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H A Dcache-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7m.S
5 * Based on linux/arch/arm/mm/cache-v7.S
19 #include "proc-macros.S"
21 .arch armv7-m
50 * dcisw: Invalidate data cache by set/way
57 * dccisw: Clean and invalidate data cache by set/way
131 and r3, r1, r0, lsr #3 @ NumWays - 1
139 1: sub r2, r2, #1 @ NumSets--
141 2: subs r3, r3, #1 @ Temp--
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H A Dcache-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7.S
15 #include <asm/hardware/cache-b15-rac.h>
17 #include "proc-macros.S"
19 .arch armv7-a
24 .align 2
43 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
51 mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...]
53 moveq r1, #1 @ r1 needs value > 0 even if only 1 way
61 2: mov ip, r0, lsl r2 @ NumSet << SetShift
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/openbmc/linux/arch/arc/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
175 * Flush the entire MM for userland. The fastest way is to move to Next ASID
185 if (atomic_read(&mm->mm_users) == 0) in local_flush_tlb_mm()
189 * - Move to a new ASID, but only if the mm is still wired in in local_flush_tlb_mm()
190 * (Android Binder ended up calling this for vma->mm != tsk->mm, in local_flush_tlb_mm()
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/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-l2c.h7 * Copyright (c) 2003-2017 Cavium, Inc.
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
72 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
131 CVMX_L2C_TAD_EVENT_TAG_MISS = 2,
183 * Return the L2 Cache way partitioning for a given core.
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/openbmc/linux/arch/powerpc/mm/nohash/
H A Dtlb_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
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/openbmc/linux/arch/mips/mm/
H A Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
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/openbmc/u-boot/doc/
H A DREADME.N12137 - 16-/32-bit mixable instruction format.
8 - 32 general-purpose 32-bit registers.
9 - 8-stage pipeline.
10 - Dynamic branch prediction.
11 - 32/64/128/256 BTB.
12 - Return address stack (RAS).
13 - Vector interrupts for internal/external.
15 - 3 HW-level nested interruptions.
16 - User and super-user mode support.
17 - Memory-mapped I/O.
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/openbmc/linux/Documentation/admin-guide/
H A Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
49 2 block Floppy disks
52 2 = /dev/fd2 Controller 0, drive 2, autodetect
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/openbmc/linux/arch/arm/include/asm/
H A Dv7m.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2)
25 #define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
49 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
50 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
53 #define EXC_RET_THREADMODE_PROCESSSTACK (3 << 2)
62 /* Memory-mapped MPU registers for M-class */
66 #define MPU_CTRL_PRIVDEFENA (1 << 2)
81 #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
82 #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
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/openbmc/linux/Documentation/devicetree/bindings/mux/
H A Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
20 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
21 0-7 for an 8-way multiplexer, etc.
25 --------------------
28 specifier using the '#mux-control-cells' or '#mux-state-cells' property.
29 The value of '#mux-state-cells' will always be one greater than the value
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/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dsubcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
37 * ------------|------------------
39 * 2-way split | 2
40 * 4-way split | 4
46 * ----------------------------
48 * ----------------------------
49 * Thread | 0 1 2 3 4 5 6 7 |
50 * ----------------------------
52 * 2-way split:
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/openbmc/linux/arch/sh/mm/
H A Dcache-sh2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh2.c
23 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
24 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_wback_region()
25 & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
28 int way; in sh2__flush_wback_region() local
29 for (way = 0; way < 4; way++) { in sh2__flush_wback_region()
30 unsigned long data = __raw_readl(addr | (way << 12)); in sh2__flush_wback_region()
33 __raw_writel(data, addr | (way << 12)); in sh2__flush_wback_region()
44 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_purge_region()
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