cpu/armv7/cache_v7_asm.S

1 /* SPDX-License-Identifier: GPL-2.0+ */
19  *	Flush the whole D-cache.
21  *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
23  *	Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
29 	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
37 	cmp	r1, #2				@ see what cache we have at this level
38 	blt	skip				@ skip if no cache, or just i-cache
39 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
45 	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
46 	clz	r5, r4				@ find bit position of way size increment
52  ARM(	orr	r11, r10, r4, lsl r5	)	@ factor way and cache number into r11
54  THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
58 	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
61 	subs	r4, r4, #1			@ decrement the way
64 	add	r10, r10, #2			@ increment cache number
69 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
76  ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
77  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
79  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
80  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
87  *	Invalidate the whole D-cache.
89  *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
92  *	mcr     p15, 0, r11, c7, c14, 2
94  *	mcr     p15, 0, r11, c7, c6, 2
100 	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
107 	cmp	r1, #2				@ see what cache we have at this level
108 	blt	inval_skip			@ skip if no cache, or just i-cache
109 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
115 	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
116 	clz	r5, r4				@ find bit position of way size increment
122  ARM(	orr	r11, r10, r4, lsl r5	)	@ factor way and cache number into r11
124  THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
128 	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
131 	subs	r4, r4, #1			@ decrement the way
134 	add	r10, r10, #2			@ increment cache number
139 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
146  ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
147  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
149  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
150  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)