Home
last modified time | relevance | path

Searched +full:1 +full:_chan (Results 1 – 25 of 40) sorted by relevance

12

/openbmc/linux/sound/pci/hda/
H A Dca0132_regs.h33 #define XRAM_XRAM_INST_OFFSET(_chan) \ argument
35 (_chan * XRAM_XRAM_CHAN_INCR))
41 #define YRAM_YRAM_INST_OFFSET(_chan) \ argument
43 (_chan * YRAM_YRAM_CHAN_INCR))
49 #define UC_UC_INST_OFFSET(_chan) \ argument
51 (_chan * UC_UC_CHAN_INCR))
57 #define AXRAM_AXRAM_INST_OFFSET(_chan) \ argument
59 (_chan * AXRAM_AXRAM_CHAN_INCR))
65 #define AYRAM_AYRAM_INST_OFFSET(_chan) \ argument
67 (_chan * AYRAM_AYRAM_CHAN_INCR))
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.h63 * | port 0 | port 1 | port 2 | port 3 | port 4 | port 5 | port 6 | port 7 |
72 * | register block for quad 0 | register block for quad 1 |
74 * ||port 0|port 1|port 2|port 3|||port 0|port 1|port 2|port 3||
81 * * PHY port 5 is port 1 in quad 1
143 u8 init : 1;
144 u8 calibrating : 1;
145 u8 verify_cached : 1;
239 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) argument
240 #define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8)) argument
241 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8)) argument
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dltc2497-core.c46 return 1; in ltc2497core_wait_conv()
99 *val2 = ddata->chip_info->resolution + 1; in ltc2497core_read_raw()
108 #define LTC2497_CHAN(_chan, _addr, _ds_name) { \ argument
110 .indexed = 1, \
111 .channel = (_chan), \
112 .address = (_addr | (_chan / 2) | ((_chan & 1) ? LTC2497_SIGN : 0)), \
118 #define LTC2497_CHAN_DIFF(_chan, _addr) { \ argument
120 .indexed = 1, \
121 .channel = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 1 : 0), \
122 .channel2 = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 0 : 1),\
[all …]
H A Dad7266.c60 return spi_read(st->spi, &st->data.sample[0], 1); in ad7266_powerdown()
107 nr >>= 1; in ad7266_select_input()
110 nr |= 1; in ad7266_select_input()
113 nr &= ~1; in ad7266_select_input()
165 chan->scan_type.realbits - 1); in ad7266_read_raw()
189 #define AD7266_CHAN(_chan, _sign) { \ argument
191 .indexed = 1, \
192 .channel = (_chan), \
193 .address = (_chan), \
197 .scan_index = (_chan), \
[all …]
H A Dmeson_saradc.c44 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
49 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \ argument
50 (GENMASK(2, 0) << ((_chan) * 3))
53 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \ argument
54 (16 + ((_chan) * 2))
55 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \ argument
56 (GENMASK(17, 16) << ((_chan) * 2))
57 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \ argument
58 (0 + ((_chan) * 2))
59 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \ argument
[all …]
H A Dxilinx-xadc-core.c111 #define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
114 * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
116 * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
179 uint32_t cmd[1]; in xadc_zynq_write_adc_reg()
218 cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0); in xadc_zynq_read_adc_reg()
229 tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET; in xadc_zynq_read_adc_reg()
251 ((alarm & 0x78) << 1) | in xadc_zynq_transform_alarm()
437 alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07); in xadc_zynq_update_alarm()
525 events = (status & 0x000e) >> 1; in xadc_axi_interrupt_handler()
547 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) | in xadc_axi_update_alarm()
[all …]
H A Dti-ads7924.c58 * Register address INC bit: when set to '1', the register address is
66 #define ADS7924_MODECNTRL_SEL_MASK GENMASK(1, 0)
68 #define ADS7924_CFG_INTPOL_BIT 1
76 #define ADS7924_CFG_INTPOL_HIGH 1
80 #define ADS7924_CFG_INTTRIG_EDGE 1
122 #define ADS7924_V_CHAN(_chan, _addr) { \ argument
124 .indexed = 1, \
125 .channel = _chan, \
129 .datasheet_name = "AIN"#_chan, \
187 ADS7924_V_CHAN(1, ADS7924_DATA1_U_REG),
[all …]
H A Dti-ads1015.c50 #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
64 #define ADS1015_CFG_COMP_POL_HIGH 1
68 #define ADS1015_CFG_COMP_MODE_WINDOW 1
72 #define ADS1015_SINGLESHOT 1
140 static const int ads1015_comp_queue[] = { 1, 2, 4 };
166 * constant _fitbits by constant 1 in each successful compilation case.
182 #define ADS1015_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \ argument
184 .indexed = 1, \
186 .channel = _chan, \
203 .datasheet_name = "AIN"#_chan, \
[all …]
H A Dad7292.c42 #define AD7292_VOLTAGE_CHAN(_chan) \ argument
47 .indexed = 1, \
48 .channel = _chan, \
53 AD7292_VOLTAGE_CHAN(1),
66 .indexed = 1,
67 .differential = 1,
69 .channel2 = 1,
94 ret = spi_write_then_read(st->spi, st->d8, 1, &st->d16, 2); in ad7292_spi_reg_read()
108 st->d8[1] = sub_addr; in ad7292_spi_subreg_read()
137 st->d8[1] = AD7292_RD_FLAG_MSK(AD7292_REG_CONV_COMM); in ad7292_single_conversion()
[all …]
H A Dad7291.c54 #define AD7291_RESET BIT(1)
72 #define AD7291_T_HIGH BIT(1)
76 #define AD7291_V_HIGH(x) BIT((x) * 2 + 1)
261 return 1; in ad7291_read_event_config()
423 #define AD7291_VOLTAGE_CHAN(_chan) \ argument
428 .indexed = 1, \
429 .channel = _chan, \
436 AD7291_VOLTAGE_CHAN(1),
448 .indexed = 1,
H A Dad9467.c130 unsigned char tbuf[2], rbuf[1]; in ad9467_spi_read()
134 tbuf[1] = reg & 0xFF; in ad9467_spi_read()
152 buf[1] = reg & 0xFF; in ad9467_spi_write()
211 #define AD9467_CHAN(_chan, _si, _bits, _sign) \ argument
214 .indexed = 1, \
215 .channel = _chan, \
284 if (vref_val == info->scale_table[i][1]) in ad9467_get_scale()
307 __ad9467_get_scale(st, i, &scale_val[0], &scale_val[1]); in ad9467_set_scale()
308 if (scale_val[0] != val || scale_val[1] != val2) in ad9467_set_scale()
313 info->scale_table[i][1]); in ad9467_set_scale()
[all …]
/openbmc/u-boot/drivers/adc/
H A Dmeson-saradc.c39 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
44 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \ argument
45 (GENMASK(2, 0) << ((_chan) * 3))
48 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \ argument
49 (16 + ((_chan) * 2))
50 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \ argument
51 (GENMASK(17, 16) << ((_chan) * 2))
52 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \ argument
53 (0 + ((_chan) * 2))
54 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \ argument
[all …]
/openbmc/linux/drivers/input/touchscreen/
H A Dtsc2007_iio.c15 #define TSC2007_CHAN_IIO(_chan, _name, _type, _chan_info) \ argument
21 .indexed = 1, \
22 .channel = _chan, \
27 TSC2007_CHAN_IIO(1, "y", IIO_VOLTAGE, IIO_CHAN_INFO_RAW),
58 case 1: in tsc2007_read_raw()
/openbmc/linux/drivers/iio/dac/
H A Dad5624r_spi.c72 if (val >= (1 << chan->scan_type.realbits) || val < 0) in ad5624r_write_raw()
85 "1kohm_to_gnd",
121 !!(st->pwr_down_mask & (1 << chan->channel))); in ad5624r_read_dac_powerdown()
137 st->pwr_down_mask |= (1 << chan->channel); in ad5624r_write_dac_powerdown()
139 st->pwr_down_mask &= ~(1 << chan->channel); in ad5624r_write_dac_powerdown()
166 #define AD5624R_CHANNEL(_chan, _bits) { \ argument
168 .indexed = 1, \
169 .output = 1, \
170 .channel = (_chan), \
173 .address = (_chan), \
[all …]
H A Dad5504.c31 #define AD5504_ADDR_DAC(x) ((x) + 1)
39 #define AD5504_DAC_PWRDN_3STATE 1
81 .rx_buf = &st->data[1], in ad5504_spi_read()
86 ret = spi_sync_transfer(st->spi, &t, 1); in ad5504_spi_read()
90 return be16_to_cpu(st->data[1]) & AD5504_RES_MASK; in ad5504_spi_read()
129 if (val >= (1 << chan->scan_type.realbits) || val < 0) in ad5504_write_raw()
174 !(st->pwr_down_mask & (1 << chan->channel))); in ad5504_read_dac_powerdown()
190 st->pwr_down_mask &= ~(1 << chan->channel); in ad5504_write_dac_powerdown()
192 st->pwr_down_mask |= (1 << chan->channel); in ad5504_write_dac_powerdown()
205 static IIO_CONST_ATTR(temp0_thresh_rising_en, "1");
[all …]
H A Dad5764.c75 #define AD5764_CHANNEL(_chan, _bits) { \ argument
77 .indexed = 1, \
78 .output = 1, \
79 .channel = (_chan), \
80 .address = (_chan), \
97 AD5764_CHANNEL(1, (_bits)), \
133 ret = spi_write(st->spi, &st->data[0].d8[1], 3); in ad5764_write()
146 .tx_buf = &st->data[0].d8[1], in ad5764_read()
148 .cs_change = 1, in ad5764_read()
150 .rx_buf = &st->data[1].d8[1], in ad5764_read()
[all …]
H A Dad5766.c21 #define AD5766_DITHER_SOURCE_MASK(ch) GENMASK(((2 * ch) + 1), (2 * ch))
86 "1",
101 * 0 - Normal operation, 1 - Power down
105 * 1: N0, 2: N1
108 * 0: 1 SCALING, 1: 0.75 SCALING, 2: 0.5 SCALING,
153 .cs_change = 1, in __ad5766_spi_read()
155 .tx_buf = &st->data[1].d32, in __ad5766_spi_read()
163 st->data[1].d32 = AD5766_CMD_NOP_MUX_OUT; in __ad5766_spi_read()
169 *val = st->data[2].w16[1]; in __ad5766_spi_read()
177 put_unaligned_be16(data, &st->data[0].b8[1]); in __ad5766_spi_write()
[all …]
H A Dltc2632.c120 if (val >= (1 << chan->scan_type.realbits) || val < 0) in ltc2632_write_raw()
140 !!(st->powerdown_cache_mask & (1 << chan->channel))); in ltc2632_read_dac_powerdown()
158 st->powerdown_cache_mask |= (1 << chan->channel); in ltc2632_write_dac_powerdown()
160 st->powerdown_cache_mask &= ~(1 << chan->channel); in ltc2632_write_dac_powerdown()
184 #define LTC2632_CHANNEL(_chan, _bits) { \ argument
186 .indexed = 1, \
187 .output = 1, \
188 .channel = (_chan), \
191 .address = (_chan), \
202 LTC2632_CHANNEL(1, _bits), \
/openbmc/linux/Documentation/devicetree/bindings/dma/ti/
H A Dk3-pktdma.yaml64 minItems: 1
75 minItems: 1
86 minItems: 1
97 minItems: 1
169 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
170 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
/openbmc/linux/drivers/iio/cdc/
H A Dad7150.c3 * AD7150 capacitive sensor driver supporting AD7150/1/6
27 #define AD7150_CH1_DATA_HIGH_REG 1
122 ad7150_addresses[channel][1]); in ad7150_read_raw()
141 /* Strangely same for both 1 and 2 chan parts */ in ad7150_read_raw()
220 chip->thresh_timeout[1][chan]); in ad7150_write_event_params()
270 disable_irq(chip->interrupts[1]); in ad7150_write_event_config()
281 fixed = 1; in ad7150_write_event_config()
311 enable_irq(chip->interrupts[1]); in ad7150_write_event_config()
437 #define AD7150_CAPACITANCE_CHAN(_chan) { \ argument
439 .indexed = 1, \
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Ddas6402.c22 * [1] - IRQ (optional, needed for async command support)
43 #define DAS6402_STATUS_FHALF BIT(1)
51 #define DAS6402_STATUS_W_CLRXTR BIT(1)
60 #define DAS6402_CTRL_EXT_FALL_TRIG DAS6402_CTRL_TRIG(1)
69 #define DAS6402_TRIG_TGSEL BIT(1)
72 #define DAS6402_AO_RANGE(_chan, _range) ((_range) << ((_chan) ? 6 : 4)) argument
73 #define DAS6402_AO_RANGE_MASK(_chan) (3 << ((_chan) ? 6 : 4)) argument
77 #define DAS6402_MODE_FIFONEPTY DAS6402_MODE_RANGE(1)
85 #define DAS6402_MODE_DMA3 DAS6402_MODE_DMA(1)
190 comedi_buf_write_samples(s, &val, 1); in das6402_interrupt()
[all …]
/openbmc/linux/drivers/dma/
H A Dfsl-edma-main.c63 edma_writel_chreg(fsl_chan, 1, ch_int); in fsl_edma3_tx_handler()
102 struct dma_chan *chan, *_chan; in fsl_edma_xlate() local
111 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { in fsl_edma_xlate()
119 fsl_chan->slave_id = dma_spec->args[1]; in fsl_edma_xlate()
135 struct dma_chan *chan, *_chan; in fsl_edma3_xlate() local
146 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, in fsl_edma3_xlate()
155 fsl_chan->priority = dma_spec->args[1]; in fsl_edma3_xlate()
272 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. in fsl_edma2_irq_init()
283 if (i == count - 1) in fsl_edma2_irq_init()
335 .dmamuxs = 1,
[all...]
H A Dat_hdmac.c53 #define AT_DMA_SSREQ(x) BIT((x) << 1) /* Request a source single transfer on channel x */
54 #define AT_DMA_DSREQ(x) BIT(1 + ((x) << 1)) /* Request a destination single transfer on channel x …
58 #define AT_DMA_SCREQ(x) BIT((x) << 1) /* Request a source chunk transfer on channel x */
59 #define AT_DMA_DCREQ(x) BIT(1 + ((x) << 1)) /* Request a destination chunk transfer on channel x */
63 #define AT_DMA_SLAST(x) BIT((x) << 1) /* This src rq is last tx of buffer on channel x */
64 #define AT_DMA_DLAST(x) BIT(1 + ((x) << 1)) /* This dst rq is last tx of buffer on channel x */
115 #define ATC_DSCR_IF GENMASK(1, 0) /* Dsc feched via AHB-Lite Interface */
127 #define ATC_SIF GENMASK(1, 0) /* Src tx done via AHB-Lite Interface i */
130 #define AT_DMA_PER_IF 0x1 /* interface 1 as peripheral interface */
253 ATC_IS_PAUSED = 1,
[all …]
/openbmc/ipmitool/include/ipmitool/
H A Dipmi_sdr.h48 #define tos32(val, bits) ((val & ((1<<((bits)-1)))) ? (-((val) & (1<<((bits)-1))) | (val)) : (va…
85 #define SDR_SENSOR_STAT_LO_NC (1<<0)
86 #define SDR_SENSOR_STAT_LO_CR (1<<1)
87 #define SDR_SENSOR_STAT_LO_NR (1<<2)
88 #define SDR_SENSOR_STAT_HI_NC (1<<3)
89 #define SDR_SENSOR_STAT_HI_CR (1<<4)
90 #define SDR_SENSOR_STAT_HI_NR (1<<5)
107 #pragma pack(1)
122 #pragma pack(1)
135 #pragma pack(1)
[all …]
/openbmc/linux/drivers/regulator/
H A Dmax5970-regulator.c239 #define MAX597X_SWITCH(_ID, _ereg, _chan, _supply) { \ argument
249 .enable_mask = CHXEN((_chan)), \
255 MAX597X_SWITCH(sw1, MAX5970_REG_CHXEN, 1, "vss2"),
295 *dev_mask |= 1 << i; in max597x_irq_handler()
299 *dev_mask |= 1 << i; in max597x_irq_handler()
313 *dev_mask |= 1 << i; in max597x_irq_handler()
317 *dev_mask |= 1 << i; in max597x_irq_handler()
331 *dev_mask |= 1 << i; in max597x_irq_handler()
346 *dev_mask |= 1 << i; in max597x_irq_handler()
374 case 1: in max597x_adc_range()

12