63  *  | port 0 | port 1 | port 2 | port 3 | port 4 | port 5 | port 6 | port 7 |
72  * |  register block for quad 0  |  register block for quad 1  |
74  * ||port 0|port 1|port 2|port 3|||port 0|port 1|port 2|port 3||
81  *   * PHY port 5 is port 1 in quad 1
143 	u8 init : 1;
144 	u8 calibrating : 1;
145 	u8 verify_cached : 1;
239 #define GLTSYN_AUX_OUT(_chan, _idx)	(GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))  argument
240 #define GLTSYN_AUX_IN(_chan, _idx)	(GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8))  argument
241 #define GLTSYN_CLKO(_chan, _idx)	(GLTSYN_CLKO_0(_idx) + ((_chan) * 8))  argument
242 #define GLTSYN_TGT_L(_chan, _idx)	(GLTSYN_TGT_L_0(_idx) + ((_chan) * 16))  argument
243 #define GLTSYN_TGT_H(_chan, _idx)	(GLTSYN_TGT_H_0(_idx) + ((_chan) * 16))  argument
244 #define GLTSYN_EVNT_L(_chan, _idx)	(GLTSYN_EVNT_L_0(_idx) + ((_chan) * 16))  argument
245 #define GLTSYN_EVNT_H(_chan, _idx)	(GLTSYN_EVNT_H_0(_idx) + ((_chan) * 16))  argument
293 	return -1;  in ice_get_ptp_clock_index()
300 	return -1;  in ice_ptp_request_ts()