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/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dlowlevel_init.S21 stp x1, x2, [x0], #16
22 stp x3, x4, [x0], #16
23 stp x5, x6, [x0], #16
24 stp x7, x8, [x0], #16
25 stp x9, x10, [x0], #16
26 stp x11, x12, [x0], #16
27 stp x13, x14, [x0], #16
28 stp x15, x16, [x0], #16
29 stp x17, x18, [x0], #16
30 stp x19, x20, [x0], #16
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx25.h74 * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes)
82 * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers
83 * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX
84 * 0x43F0_8000 0x43F0_BFFF 16 Kbytes ARM926 platform CLKCTL
85 * 0x43F0_C000 0x43F0_FFFF 16 Kbytes ARM926 platform ETB registers
86 * 0x43F1_0000 0x43F1_3FFF 16 Kbytes ARM926 platform ETB memory
87 * 0x43F1_4000 0x43F1_7FFF 16 Kbytes ARM926 platform AAPE registers
89 * 0x43F8_0000 0x43F8_3FFF 16 Kbytes I2C-1
90 * 0x43F8_4000 0x43F8_7FFF 16 Kbytes I2C-3
91 * 0x43F8_8000 0x43F8_BFFF 16 Kbytes CAN-1
[all …]
/openbmc/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc5 F2(RI_a, R(1, 8), I(2,16,16))
6 F2(RI_b, R(1, 8), I(2,16,16))
7 F2(RI_c, M(1, 8), I(2,16,16))
8 F3(RIE_a, R(1, 8), I(2,16,16), M(3,32))
9 F4(RIE_b, R(1, 8), R(2,12), M(3,32), I(4,16,16))
10 F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16))
11 F3(RIE_d, R(1, 8), I(2,16,16), R(3,12))
12 F3(RIE_e, R(1, 8), I(2,16,16), R(3,12))
13 F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
14 F3(RIE_g, R(1, 8), I(2,16,16), M(3,12))
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dexceptions.S25 * Each of those 16 entries have space for 32 instructions, each entry must
39 stp x29, x30, [sp, #-16]!
49 stp x27, x28, [sp, #-16]!
50 stp x25, x26, [sp, #-16]!
51 stp x23, x24, [sp, #-16]!
52 stp x21, x22, [sp, #-16]!
53 stp x19, x20, [sp, #-16]!
54 stp x17, x18, [sp, #-16]!
55 stp x15, x16, [sp, #-16]!
56 stp x13, x14, [sp, #-16]!
[all …]
/openbmc/qemu/hw/audio/
H A Dgustate.h43 #define VSRegsEnd (VSRControl+VSRegs + 32*(16*2))
51 #define VSRVolRampEndVol (16)
61 #define wVSRegsEnd (wVSRControl+wVSRegs + 32*(16))
83 #define RegCtrl_2xF (VSRVolRampControl+2+(16*2))
84 #define Jumper_2xB (VSRVolRampControl+2+(16*2)+1)
85 #define GUS42DMAStart (VSRVolRampControl+2+(16*2)+2)
87 #define GUS43DRAMIOlo (VSRVolRampControl+2+(16*2)*2)
89 #define GUS44DRAMIOhi (VSRVolRampControl+2+(16*2)*2+2)
91 #define voicewavetableirq (VSRVolRampControl+2+(16*2)*3) /* voice IRQ pseudoqueue: 1 bit per voice …
93 #define voicevolrampirq (VSRVolRampControl+2+(16*2)*4) /* voice IRQ pseudoqueue: 1 bit per voice …
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dat-All10 MODULATION = QAM/16
22 MODULATION = QAM/16
34 MODULATION = QAM/16
46 MODULATION = QAM/16
58 MODULATION = QAM/16
70 MODULATION = QAM/16
82 MODULATION = QAM/16
94 MODULATION = QAM/16
106 MODULATION = QAM/16
118 MODULATION = QAM/16
[all …]
H A Dch-All10 MODULATION = QAM/16
22 MODULATION = QAM/16
34 MODULATION = QAM/16
46 MODULATION = QAM/16
58 MODULATION = QAM/16
70 MODULATION = QAM/16
82 MODULATION = QAM/16
94 MODULATION = QAM/16
106 MODULATION = QAM/16
118 MODULATION = QAM/16
[all …]
H A Dlt-All14 GUARD_INTERVAL = 1/16
26 GUARD_INTERVAL = 1/16
38 GUARD_INTERVAL = 1/16
50 GUARD_INTERVAL = 1/16
62 GUARD_INTERVAL = 1/16
74 GUARD_INTERVAL = 1/16
86 GUARD_INTERVAL = 1/16
98 GUARD_INTERVAL = 1/16
110 GUARD_INTERVAL = 1/16
124 GUARD_INTERVAL = 1/16
[all …]
H A Dau-Bendigo11 GUARD_INTERVAL = 1/16
23 GUARD_INTERVAL = 1/16
35 GUARD_INTERVAL = 1/16
49 GUARD_INTERVAL = 1/16
61 GUARD_INTERVAL = 1/16
73 GUARD_INTERVAL = 1/16
87 GUARD_INTERVAL = 1/16
99 GUARD_INTERVAL = 1/16
113 GUARD_INTERVAL = 1/16
165 GUARD_INTERVAL = 1/16
[all …]
H A Dde-Niedersachsen9 MODULATION = QAM/16
21 MODULATION = QAM/16
34 MODULATION = QAM/16
46 MODULATION = QAM/16
58 MODULATION = QAM/16
70 MODULATION = QAM/16
82 MODULATION = QAM/16
94 MODULATION = QAM/16
106 MODULATION = QAM/16
118 MODULATION = QAM/16
[all …]
H A Dde-Hessen9 MODULATION = QAM/16
21 MODULATION = QAM/16
33 MODULATION = QAM/16
45 MODULATION = QAM/16
57 MODULATION = QAM/16
69 MODULATION = QAM/16
81 MODULATION = QAM/16
93 MODULATION = QAM/16
105 MODULATION = QAM/16
117 MODULATION = QAM/16
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dtest-aes.c8 asm("ld1 { v0.16b }, [%1]\n\t" in test_SB_SR()
9 "movi v1.16b, #0\n\t" in test_SB_SR()
10 "aese v0.16b, v1.16b\n\t" in test_SB_SR()
11 "st1 { v0.16b }, [%0]" in test_SB_SR()
18 asm("ld1 { v0.16b }, [%1]\n\t" in test_MC()
19 "aesmc v0.16b, v0.16b\n\t" in test_MC()
20 "st1 { v0.16b }, [%0]" in test_MC()
33 asm("ld1 { v0.16b }, [%1]\n\t" in test_ISB_ISR()
34 "movi v1.16b, #0\n\t" in test_ISB_ISR()
35 "aesd v0.16b, v1.16b\n\t" in test_ISB_ISR()
[all …]
/openbmc/u-boot/arch/arm/include/asm/mach-imx/
H A Dregs-gpmi.h58 #define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
62 #define GPMI_COMPARE_MASK_MASK (0xffff << 16)
63 #define GPMI_COMPARE_MASK_OFFSET 16
67 #define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16)
68 #define GPMI_ECCCTRL_HANDLE_OFFSET 16
95 #define GPMI_CTRL1_HALF_PERIOD (1 << 16)
110 #define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
111 #define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
117 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16)
118 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16
[all …]
/openbmc/u-boot/drivers/serial/
H A Dserial_sh.h26 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
71 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
72 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
73 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
77 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
83 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
84 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
85 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
[all …]
/openbmc/u-boot/include/
H A Dflash.h128 #define ERR_ALIGN 16
194 /* 8 Mbit, 512K x 16, */
195 /* 8 64K x 16 uniform sectors */
202 #define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
213 #define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */
214 #define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
216 #define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */
217 #define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
267 #define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
268 #define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-timrot.h60 #define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16)
61 #define TIMROT_ROTCTRL_DIVIDER_OFFSET 16
163 #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16)
164 #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16
183 #define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16)
184 #define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16
185 #define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16)
186 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16)
187 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16)
188 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16)
[all …]
H A Dregs-uartapp.h37 #define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
38 #define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16)
66 #define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16
67 #define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16)
68 #define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16)
69 #define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16)
70 #define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16)
71 #define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16)
72 #define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16)
73 #define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16)
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-queensbay/fsp/
H A Dfsp_vpd.h18 u8 hda_verb_data0[16]; /* Offset 0x0110 */
19 u8 hda_verb_data1[16]; /* Offset 0x0120 */
20 u8 hda_verb_data2[16]; /* Offset 0x0130 */
21 u8 hda_verb_data3[16]; /* Offset 0x0140 */
22 u8 hda_verb_data4[16]; /* Offset 0x0150 */
23 u8 hda_verb_data5[16]; /* Offset 0x0160 */
24 u8 hda_verb_data6[16]; /* Offset 0x0170 */
25 u8 hda_verb_data7[16]; /* Offset 0x0180 */
26 u8 hda_verb_data8[16]; /* Offset 0x0190 */
27 u8 hda_verb_data9[16]; /* Offset 0x01A0 */
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D049.out7 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
10 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
13 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
16 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
19 …r_size=65536 extended_l2=off compression_type=zlib size=1048576 lazy_refcounts=off refcount_bits=16
22 …ize=65536 extended_l2=off compression_type=zlib size=1073741824 lazy_refcounts=off refcount_bits=16
25 …=65536 extended_l2=off compression_type=zlib size=1099511627776 lazy_refcounts=off refcount_bits=16
28 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
31 …ster_size=65536 extended_l2=off compression_type=zlib size=1024 lazy_refcounts=off refcount_bits=16
34 …ster_size=65536 extended_l2=off compression_type=zlib size=1536 lazy_refcounts=off refcount_bits=16
[all …]
/openbmc/ipmitool/src/plugins/lan/
H A Dauth.c69 static uint8_t md[16]; in ipmi_auth_md5()
77 memset(md, 0, 16); in ipmi_auth_md5()
81 MD5_Update(&ctx, (const uint8_t *)s->authcode, 16); in ipmi_auth_md5()
85 MD5_Update(&ctx, (const uint8_t *)s->authcode, 16); in ipmi_auth_md5()
89 printf(" MD5 AuthCode : %s\n", buf2str(md, 16)); in ipmi_auth_md5()
94 static md5_byte_t digest[16]; in ipmi_auth_md5()
97 memset(digest, 0, 16); in ipmi_auth_md5()
102 md5_append(&state, (const md5_byte_t *)s->authcode, 16); in ipmi_auth_md5()
112 md5_append(&state, (const md5_byte_t *)s->authcode, 16); in ipmi_auth_md5()
117 printf(" MD5 AuthCode : %s\n", buf2str(digest, 16)); in ipmi_auth_md5()
[all …]
/openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/python3-inotify/
H A Dnew-test-inotify.patch39 @@ -15,6 +16,11 @@ except NameError:
69 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=256, cookie=0, len=16), ['IN_CREATE'],…
70 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=32, cookie=0, len=16), ['IN_OPEN'], in…
71 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=8, cookie=0, len=16), ['IN_CLOSE_WRITE…
72 + (inotify.adapters._INOTIFY_EVENT(wd=wd, mask=256, cookie=0, len=16), ['IN_CREATE']…
73 + (inotify.adapters._INOTIFY_EVENT(wd=wd, mask=32, cookie=0, len=16), ['IN_OPEN'], i…
74 + (inotify.adapters._INOTIFY_EVENT(wd=wd, mask=8, cookie=0, len=16), ['IN_CLOSE_WRIT…
110 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=256, cookie=0, len=16), ['IN_CREATE'],…
111 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=32, cookie=0, len=16), ['IN_OPEN'], in…
112 - (inotify.adapters._INOTIFY_EVENT(wd=1, mask=8, cookie=0, len=16), ['IN_CLOSE_WRITE…
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c83 LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS),
84 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
85 LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, SZ_16K, SP_OPTIONS16),
86 LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, SZ_16K, SP_OPTIONS16),
90 LEGACY_ID_NAND("NAND 32MiB 1,8V 16-bit", 0x45, 32, SZ_16K, SP_OPTIONS16),
91 LEGACY_ID_NAND("NAND 32MiB 3,3V 16-bit", 0x55, 32, SZ_16K, SP_OPTIONS16),
95 LEGACY_ID_NAND("NAND 64MiB 1,8V 16-bit", 0x46, 64, SZ_16K, SP_OPTIONS16),
96 LEGACY_ID_NAND("NAND 64MiB 3,3V 16-bit", 0x56, 64, SZ_16K, SP_OPTIONS16),
101 LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x72, 128, SZ_16K, SP_OPTIONS16),
102 LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x49, 128, SZ_16K, SP_OPTIONS16),
[all …]
/openbmc/qemu/tests/tcg/alpha/system/
H A Dboot.S53 mov $gp, $16
57 ldah $16, entInt($gp) !gprelhigh
58 lda $16, entInt($16) !gprellow
62 ldah $16, entArith($gp) !gprelhigh
63 lda $16, entArith($16) !gprellow
67 ldah $16, entMM($gp) !gprelhigh
68 lda $16, entMM($16) !gprellow
72 ldah $16, entIF($gp) !gprelhigh
73 lda $16, entIF($16) !gprellow
77 ldah $16, entUna($gp) !gprelhigh
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9263_matrix.h18 * 16 masters and 16 slaves.
22 u32 mcfg[16]; /* Master Configuration Registers */
23 u32 scfg[16]; /* Slave Configuration Registers */
24 u32 pras[16][2]; /* Priority Assignment Slave Registers */
38 #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
39 #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
40 #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
49 #define AT91_MATRIX_M4PR_SHIFT 16
60 #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
61 #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
/openbmc/u-boot/drivers/video/tegra124/
H A Dsor.h97 #define NV_HEAD_STATE1_VTOTAL_SHIFT 16
98 #define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16)
102 #define NV_HEAD_STATE2_VSYNC_END_SHIFT 16
103 #define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16)
107 #define NV_HEAD_STATE3_VBLANK_END_SHIFT 16
108 #define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16)
112 #define NV_HEAD_STATE4_VBLANK_START_SHIFT 16
113 #define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16)
162 #define PWR_SAFE_STATE_SHIFT 16
163 #define PWR_SAFE_STATE_DEFAULT_MASK (1 << 16)
[all …]

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