Lines Matching full:16

97 #define NV_HEAD_STATE1_VTOTAL_SHIFT			16
98 #define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16)
102 #define NV_HEAD_STATE2_VSYNC_END_SHIFT 16
103 #define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16)
107 #define NV_HEAD_STATE3_VBLANK_END_SHIFT 16
108 #define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16)
112 #define NV_HEAD_STATE4_VBLANK_START_SHIFT 16
113 #define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16)
162 #define PWR_SAFE_STATE_SHIFT 16
163 #define PWR_SAFE_STATE_DEFAULT_MASK (1 << 16)
164 #define PWR_SAFE_STATE_PD (0 << 16)
165 #define PWR_SAFE_STATE_PU (1 << 16)
168 #define PWR_NORMAL_START_NORMAL (0 << 16)
169 #define PWR_NORMAL_START_ALT (1 << 16)
181 #define TEST_TESTMUX_AVDD (16 << 24)
196 #define TEST_DSRC_SHIFT 16
197 #define TEST_DSRC_DEFAULT_MASK (3 << 16)
198 #define TEST_DSRC_NORMAL (0 << 16)
199 #define TEST_DSRC_DEBUG (1 << 16)
200 #define TEST_DSRC_TGEN (2 << 16)
292 #define CSTM_LVDS_EN_SHIFT 16
293 #define CSTM_LVDS_EN_DISABLE (0 << 16)
294 #define CSTM_LVDS_EN_ENABLE (1 << 16)
323 #define LVDS_LVDS_EN_SHIFT 16
324 #define LVDS_LVDS_EN_DEFAULT_MASK (1 << 16)
325 #define LVDS_LVDS_EN_ENABLE (1 << 16)
391 #define SEQ_CTL_PC_SHIFT 16
392 #define SEQ_CTL_PC_MASK (0xf << 16)
413 #define LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT 16
414 #define LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16)
415 #define LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16)
491 #define SEQ_INST_PDPLL_SHIFT 16
492 #define SEQ_INST_PDPLL_NO (0 << 16)
493 #define SEQ_INST_PDPLL_YES (1 << 16)
528 #define DP_LINKCTL_LANECOUNT_SHIFT 16
529 #define DP_LINKCTL_LANECOUNT_MASK (0x1f << 16)
530 #define DP_LINKCTL_LANECOUNT_ZERO (0 << 16)
531 #define DP_LINKCTL_LANECOUNT_ONE (1 << 16)
532 #define DP_LINKCTL_LANECOUNT_TWO (3 << 16)
533 #define DP_LINKCTL_LANECOUNT_FOUR (15 << 16)
558 #define DC_LANE2_DP_LANE0_SHIFT 16
559 #define DC_LANE2_DP_LANE0_MASK (0xff << 16)
560 #define DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16)
561 #define DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16)
562 #define DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16)
563 #define DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16)
564 #define DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16)
565 #define DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16)
566 #define DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16)
567 #define DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16)
568 #define DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16)
569 #define DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16)
608 #define PR_LANE2_DP_LANE0_SHIFT 16
609 #define PR_LANE2_DP_LANE0_MASK (0xff << 16)
610 #define PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16)
611 #define PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16)
612 #define PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16)
613 #define PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16)
614 #define PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16)
615 #define PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16)
616 #define PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16)
617 #define PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16)
618 #define PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16)
619 #define PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16)
659 #define DP_CONFIG_ACTIVESYM_FRAC_SHIFT 16
660 #define DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16)
690 #define DP_PADCTL_VCMMODE_SHIFT 16
691 #define DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16)
692 #define DP_PADCTL_VCMMODE_TRISTATE (0 << 16)
693 #define DP_PADCTL_VCMMODE_TEST_MUX (1 << 16)
694 #define DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16)
695 #define DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16)
771 #define DP_TPG_LANE2_PATTERN_SHIFT 16
772 #define DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16)
773 #define DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16)
774 #define DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16)
775 #define DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16)
776 #define DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16)
777 #define DP_TPG_LANE2_PATTERN_D102 (4 << 16)
778 #define DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16)
779 #define DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16)
780 #define DP_TPG_LANE2_PATTERN_CSTM (7 << 16)
781 #define DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16)