1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 23a0398d7SOtavio Salvador /* 33a0398d7SOtavio Salvador * Freescale i.MX28 TIMROT Register Definitions 43a0398d7SOtavio Salvador * 53a0398d7SOtavio Salvador * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 63a0398d7SOtavio Salvador * 73a0398d7SOtavio Salvador * Based on code from LTIB: 83a0398d7SOtavio Salvador * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 93a0398d7SOtavio Salvador */ 103a0398d7SOtavio Salvador 113a0398d7SOtavio Salvador #ifndef __MX28_REGS_TIMROT_H__ 123a0398d7SOtavio Salvador #define __MX28_REGS_TIMROT_H__ 133a0398d7SOtavio Salvador 14552a848eSStefano Babic #include <asm/mach-imx/regs-common.h> 153a0398d7SOtavio Salvador 163a0398d7SOtavio Salvador #ifndef __ASSEMBLY__ 179c471142SOtavio Salvador struct mxs_timrot_regs { 18ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_rotctrl) 19ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_rotcount) 206ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 216ecd05d2SFadil Berisha mxs_reg_32(hw_timrot_timctrl0) 226ecd05d2SFadil Berisha mxs_reg_32(hw_timrot_timcount0) 236ecd05d2SFadil Berisha mxs_reg_32(hw_timrot_timctrl1) 246ecd05d2SFadil Berisha mxs_reg_32(hw_timrot_timcount1) 256ecd05d2SFadil Berisha mxs_reg_32(hw_timrot_timctrl2) 266ecd05d2SFadil Berisha mxs_reg_32(hw_timrot_timcount2) 276ecd05d2SFadil Berisha mxs_reg_32(hw_timrot_timctrl3) 286ecd05d2SFadil Berisha mxs_reg_32(hw_timrot_timcount3) 296ecd05d2SFadil Berisha #elif defined(CONFIG_MX28) 30ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_timctrl0) 31ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_running_count0) 32ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_fixed_count0) 33ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_match_count0) 34ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_timctrl1) 35ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_running_count1) 36ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_fixed_count1) 37ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_match_count1) 38ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_timctrl2) 39ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_running_count2) 40ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_fixed_count2) 41ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_match_count2) 42ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_timctrl3) 43ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_running_count3) 44ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_fixed_count3) 45ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_match_count3) 466ecd05d2SFadil Berisha #endif 47ddcf13b1SOtavio Salvador mxs_reg_32(hw_timrot_version) 483a0398d7SOtavio Salvador }; 493a0398d7SOtavio Salvador #endif 503a0398d7SOtavio Salvador 513a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SFTRST (1 << 31) 523a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_CLKGATE (1 << 30) 533a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) 543a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) 553a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) 563a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) 573a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) 583a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) 593a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_STATE_OFFSET 22 603a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) 613a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 623a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_RELATIVE (1 << 12) 633a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) 643a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 653a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) 663a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) 673a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) 683a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) 693a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_POLARITY_B (1 << 9) 703a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_POLARITY_A (1 << 8) 716ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 726ecd05d2SFadil Berisha #define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) 736ecd05d2SFadil Berisha #elif defined(CONFIG_MX28) 743a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) 756ecd05d2SFadil Berisha #endif 763a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 773a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) 783a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) 793a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) 803a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) 813a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) 823a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) 836ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 846ecd05d2SFadil Berisha #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) 856ecd05d2SFadil Berisha #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) 866ecd05d2SFadil Berisha #elif defined(CONFIG_MX28) 873a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) 883a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) 893a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) 903a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) 913a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) 926ecd05d2SFadil Berisha #endif 936ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 946ecd05d2SFadil Berisha #define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 956ecd05d2SFadil Berisha #elif defined(CONFIG_MX28) 963a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_MASK 0xf 976ecd05d2SFadil Berisha #endif 983a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 993a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 1003a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 1013a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 1023a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 1033a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 1043a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 1056ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 1066ecd05d2SFadil Berisha #define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 1076ecd05d2SFadil Berisha #define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 1086ecd05d2SFadil Berisha #elif defined(CONFIG_MX28) 1093a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 1103a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 1113a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 1123a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 1133a0398d7SOtavio Salvador #define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa 1146ecd05d2SFadil Berisha #endif 1153a0398d7SOtavio Salvador 1163a0398d7SOtavio Salvador #define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff 1173a0398d7SOtavio Salvador #define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 1183a0398d7SOtavio Salvador 1193a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_IRQ (1 << 15) 1203a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) 1216ecd05d2SFadil Berisha #if defined(CONFIG_MX28) 1223a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) 1236ecd05d2SFadil Berisha #endif 1243a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_POLARITY (1 << 8) 1253a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_UPDATE (1 << 7) 1263a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_RELOAD (1 << 6) 1273a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) 1283a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 1293a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) 1303a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) 1313a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) 1323a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) 1333a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_MASK 0xf 1343a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_OFFSET 0 1353a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 1363a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 1373a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 1383a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 1393a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 1403a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 1416ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 1426ecd05d2SFadil Berisha #define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 1436ecd05d2SFadil Berisha #define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 1446ecd05d2SFadil Berisha #define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 1456ecd05d2SFadil Berisha #define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9 1466ecd05d2SFadil Berisha #define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa 1476ecd05d2SFadil Berisha #define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb 1486ecd05d2SFadil Berisha #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc 1496ecd05d2SFadil Berisha #elif defined(CONFIG_MX28) 1503a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 1513a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 1523a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 1533a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 1543a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa 1553a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb 1563a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc 1573a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd 1583a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe 1593a0398d7SOtavio Salvador #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf 1606ecd05d2SFadil Berisha #endif 1613a0398d7SOtavio Salvador 1626ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 1636ecd05d2SFadil Berisha #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) 1646ecd05d2SFadil Berisha #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 1656ecd05d2SFadil Berisha #elif defined(CONFIG_MX28) 1663a0398d7SOtavio Salvador #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff 1673a0398d7SOtavio Salvador #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 1686ecd05d2SFadil Berisha #endif 1693a0398d7SOtavio Salvador 1706ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 1716ecd05d2SFadil Berisha #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff 1726ecd05d2SFadil Berisha #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 1736ecd05d2SFadil Berisha #elif defined(CONFIG_MX28) 1743a0398d7SOtavio Salvador #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff 1753a0398d7SOtavio Salvador #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 1766ecd05d2SFadil Berisha #endif 1773a0398d7SOtavio Salvador 1786ecd05d2SFadil Berisha #if defined(CONFIG_MX28) 1793a0398d7SOtavio Salvador #define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff 1803a0398d7SOtavio Salvador #define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 1816ecd05d2SFadil Berisha #endif 1823a0398d7SOtavio Salvador 1833a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) 1843a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 1853a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) 1863a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) 1873a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) 1883a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) 1893a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) 1903a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) 1916ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 1926ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) 1936ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) 1946ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) 1956ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16) 1966ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) 1976ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) 1986ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) 1996ecd05d2SFadil Berisha #elif defined(CONFIG_MX28) 2003a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) 2013a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) 2023a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) 2033a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) 2043a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) 2053a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) 2063a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) 2073a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) 2083a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) 2093a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) 2106ecd05d2SFadil Berisha #endif 2116ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 2126ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_IRQ (1 << 15) 2136ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) 2146ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) 2156ecd05d2SFadil Berisha #endif 2163a0398d7SOtavio Salvador #define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) 2176ecd05d2SFadil Berisha #if defined(CONFIG_MX23) 2186ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) 2196ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 2206ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) 2216ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) 2226ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_UPDATE (1 << 7) 2236ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_RELOAD (1 << 6) 2246ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) 2256ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 2266ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) 2276ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4) 2286ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4) 2296ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4) 2306ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_MASK 0xf 2316ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_OFFSET 0 2326ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0 2336ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_PWM0 0x1 2346ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_PWM1 0x2 2356ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_PWM2 0x3 2366ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_PWM3 0x4 2376ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_PWM4 0x5 2386ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6 2396ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7 2406ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8 2416ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9 2426ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa 2436ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb 2446ecd05d2SFadil Berisha #define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc 2456ecd05d2SFadil Berisha #define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16) 2466ecd05d2SFadil Berisha #define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16 2476ecd05d2SFadil Berisha #define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff 2486ecd05d2SFadil Berisha #define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0 2496ecd05d2SFadil Berisha #endif 2503a0398d7SOtavio Salvador 2513a0398d7SOtavio Salvador #define TIMROT_VERSION_MAJOR_MASK (0xff << 24) 2523a0398d7SOtavio Salvador #define TIMROT_VERSION_MAJOR_OFFSET 24 2533a0398d7SOtavio Salvador #define TIMROT_VERSION_MINOR_MASK (0xff << 16) 2543a0398d7SOtavio Salvador #define TIMROT_VERSION_MINOR_OFFSET 16 2553a0398d7SOtavio Salvador #define TIMROT_VERSION_STEP_MASK 0xffff 2563a0398d7SOtavio Salvador #define TIMROT_VERSION_STEP_OFFSET 0 2573a0398d7SOtavio Salvador 2583a0398d7SOtavio Salvador #endif /* __MX28_REGS_TIMROT_H__ */ 259