Lines Matching full:16
60 #define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16)
61 #define TIMROT_ROTCTRL_DIVIDER_OFFSET 16
163 #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16)
164 #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16
183 #define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16)
184 #define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16
185 #define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16)
186 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16)
187 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16)
188 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16)
189 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16)
190 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16)
192 #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16)
193 #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16)
194 #define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16)
195 #define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16)
196 #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16)
197 #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16)
198 #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16)
200 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16)
201 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16)
202 #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16)
203 #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16)
204 #define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16)
205 #define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16)
206 #define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16)
207 #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16)
208 #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16)
209 #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16)
245 #define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16)
246 #define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16
253 #define TIMROT_VERSION_MINOR_MASK (0xff << 16)
254 #define TIMROT_VERSION_MINOR_OFFSET 16