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/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
22 #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1)
52 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1)
65 #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1)
108 /* Relative to priv->regmap */
110 #define MVEBU_COMPHY_CONF1_PWRUP BIT(1)
129 * A lane is described by the following bitfields:
[all …]
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
43 #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1)
129 #define PRD_TXMARGIN_MASK GENMASK(3, 1)
149 #define PIPE_REG_RESET BIT(1)
160 #define BUNDLE_PERIOD_SEL BIT(1)
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
[all …]
/openbmc/linux/drivers/net/dsa/b53/
H A Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 PEX_BUS_MODE_X1 = 1,
55 * Bus speed - one bit per SERDES line:
56 * Low speed (0) High speed (1)
68 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
69 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
70 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
71 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
72 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
73 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
19 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
61 unsigned int lpd; /* RCW lane powerdown bit */
65 { 1, 153, FSL_SRDS_BANK_1 },
95 int serdes_get_lane_idx(int lane) in serdes_get_lane_idx() argument
97 return lanes[lane].idx; in serdes_get_lane_idx()
100 int serdes_get_bank_by_lane(int lane) in serdes_get_bank_by_lane() argument
102 return lanes[lane].bank; in serdes_get_bank_by_lane()
105 int serdes_lane_enabled(int lane) in serdes_lane_enabled() argument
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H A Dmpc8536_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
75 if (!(serdes1_prtcl_map & (1 << NONE))) in is_serdes_configured()
78 ret = (1 << device) & serdes1_prtcl_map; in is_serdes_configured()
83 if (!(serdes2_prtcl_map & (1 << NONE))) in is_serdes_configured()
86 return (1 << device) & serdes2_prtcl_map; in is_serdes_configured()
96 int lane; in fsl_serdes_init() local
98 if (serdes1_prtcl_map & (1 << NONE) && in fsl_serdes_init()
99 serdes2_prtcl_map & (1 << NONE)) in fsl_serdes_init()
113 case 1: /* Lane A - SATA1, Lane E - SATA2 */ in fsl_serdes_init()
121 /* CR 1 */ in fsl_serdes_init()
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H A Dp1010_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
37 if (!(serdes1_prtcl_map & (1 << NONE))) in is_serdes_configured()
40 ret = (1 << device) & serdes1_prtcl_map; in is_serdes_configured()
45 if (!(serdes2_prtcl_map & (1 << NONE))) in is_serdes_configured()
48 return (1 << device) & serdes2_prtcl_map; in is_serdes_configured()
54 u32 pordevsr = in_be32(&gur->pordevsr); in fsl_serdes_init()
57 int lane; in fsl_serdes_init() local
59 if (serdes1_prtcl_map & (1 << NONE) && in fsl_serdes_init()
60 serdes2_prtcl_map & (1 << NONE)) in fsl_serdes_init()
69 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.c42 link->ctx->logger
52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
55 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
58 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_vs, 1); in dp_fixed_vs_pe_read_lane_adjust()
60 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
63 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_pe, 1); in dp_fixed_vs_pe_read_lane_adjust()
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
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H A Dlink_dp_training.c52 link->ctx->logger
67 switch (lt_settings->link_settings.link_rate) { in dp_log_training_result()
152 switch (lt_settings->link_settings.link_spread) { in dp_log_training_result()
168 /* TODO - DP2.0 Log: add connectivity log for FFE PRESET */ in dp_log_training_result()
172 lt_settings->link_settings.lane_count, in dp_log_training_result()
174 lt_settings->hw_lane_settings[0].VOLTAGE_SWING, in dp_log_training_result()
175 lt_settings->hw_lane_settings[0].PRE_EMPHASIS, in dp_log_training_result()
189 disable_scrabled_data_symbols = 1; in dp_initialize_scrambling_data_symbols()
305 uint32_t lane; in maximize_lane_settings() local
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings()
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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_mux.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
15 * is valid for specific lane. If the type is not valid,
16 * the function update the struct and set the type of the lane as
23 int lane, opt, valid; in comphy_mux_check_config() local
27 for (lane = 0; lane < comphy_max_lanes; in comphy_mux_check_config()
28 lane++, comphy_map_data++, mux_data++) { in comphy_mux_check_config()
30 if (comphy_map_data->type == PHY_TYPE_IGNORE) in comphy_mux_check_config()
33 mux_opt = mux_data->mux_values; in comphy_mux_check_config()
34 for (opt = 0, valid = 0; opt < mux_data->max_lane_values; in comphy_mux_check_config()
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H A Dcomphy_a3700.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
17 /* Lane 0 */
27 /* Lane 1 */
36 /* Lane 2 */
66 /* 0 1 2 3 4 5 6 7 */
67 /*-----------------------------------------------------------*/
121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
123 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
[all …]
H A Dcomphy_core.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
54 u32 lane; in comphy_print() local
56 for (lane = 0; lane < chip_cfg->comphy_lanes_count; in comphy_print()
57 lane++, comphy_map_data++) { in comphy_print()
58 if (comphy_map_data->speed == PHY_SPEED_INVALID) { in comphy_print()
59 printf("Comphy-%d: %-13s\n", lane, in comphy_print()
60 get_type_string(comphy_map_data->type)); in comphy_print()
62 printf("Comphy-%d: %-13s %-10s\n", lane, in comphy_print()
63 get_type_string(comphy_map_data->type), in comphy_print()
[all …]
H A Dcomphy_cp110.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
19 #define SD_ADDR(base, lane) (base + 0x1000 * lane) argument
20 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) argument
21 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) argument
31 * For CP-110 we have 2 Selector registers "PHY Selectors",
39 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
41 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
43 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
46 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Donnn,nb7vpq904m.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ON Semiconductor Type-C DisplayPort ALT Mode Linear Redriver
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - onnn,nb7vpq904m
18 maxItems: 1
20 vcc-supply:
23 enable-gpios: true
25 retimer-switch:
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/openbmc/u-boot/board/highbank/
H A Dahci.c1 // SPDX-License-Identifier: GPL-2.0+
81 static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) in cphy_spread_spectrum_override() argument
84 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_spread_spectrum_override()
86 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
89 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
93 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
96 static void cphy_tx_attenuation_override(u8 phy, u8 lane) in cphy_tx_attenuation_override() argument
102 shift = ((phy == 5) ? 4 : lane) * 4; in cphy_tx_attenuation_override()
109 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_tx_attenuation_override()
111 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_tx_attenuation_override()
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/openbmc/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
46 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
47 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
48 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
55 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
57 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
[all …]
H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
65 USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
67 SS_PORT_WAKEUP_EVENT(0) | SS_PORT_WAKEUP_EVENT(1) | \
72 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
73 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
74 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
75 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy_regs.h1 /* SPDX-License-Identifier: MIT
15 #define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
19 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
30 #define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
34 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
43 #define XELPDP_MSGBUS_TIMEOUT_SLOW 1
51 #define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
67 #define XELPDP_PORT_BUF_PORT_DATA_20BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
75 #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
84 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) argument
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
35 endpoint@1 { ... };
37 port@1 { ... };
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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dst,st-mipid02.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
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/openbmc/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/openbmc/linux/sound/soc/tegra/
H A Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
32 (((id) + 1) << 4) }, \
46 ASRC_STREAM_REG_DEFAULTS(1),
74 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
77 1); in tegra186_asrc_lock_stream()
84 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
85 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
95 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dmpc8610_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
33 if (!(serdes1_prtcl_map & (1 << NONE))) in is_serdes_configured()
36 ret = (1 << device) & serdes1_prtcl_map; in is_serdes_configured()
41 if (!(serdes2_prtcl_map & (1 << NONE))) in is_serdes_configured()
44 return (1 << device) & serdes2_prtcl_map; in is_serdes_configured()
50 ccsr_gur_t *gur = &immap->im_gur; in fsl_serdes_init()
51 u32 pordevsr = in_be32(&gur->pordevsr); in fsl_serdes_init()
54 int lane; in fsl_serdes_init() local
56 if (serdes1_prtcl_map & (1 << NONE) && in fsl_serdes_init()
57 serdes2_prtcl_map & (1 << NONE)) in fsl_serdes_init()
[all …]
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
13 u8 reserved008[0x10 - 0x8];
15 u32 mrctrl1; /* 0x14 Control 1*/
20 u8 reserved028[0x30 - 0x28];
24 u8 reserved03c[0x50 - 0x3C];
26 u32 reserved054; /* 0x54 Refresh Control 1*/
31 u8 reserved068[0xc0 - 0x68];
37 u32 init1; /* 0xd4 SDRAM Initialization 1*/
45 u8 reserved0f4[0x100 - 0xf4];
[all …]
/openbmc/u-boot/board/freescale/p2041rdb/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
8 * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
9 * are provided by the three on-board PHY or by the standard Freescale
10 * four-port SGMII riser card. We need to change the phy-handle in the
29 * that the mapping must be determined dynamically, or that the lane maps to
33 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
52 lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1; in initialize_lane_to_slot()
61 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
66 * ... update the phy-handle property of the Ethernet node to point to the
74 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
[all …]

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