Lines Matching +full:1 +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
19 #define SD_ADDR(base, lane) (base + 0x1000 * lane) argument
20 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) argument
21 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) argument
31 * For CP-110 we have 2 Selector registers "PHY Selectors",
39 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
41 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
43 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
46 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
48 {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
51 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
56 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
57 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
60 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
62 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
64 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
67 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
76 udelay(1); in polling_with_timeout()
78 } while (data != val && --usec_timout > 0); in polling_with_timeout()
86 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, in comphy_pcie_power_up() argument
90 u32 mask, data, ret = 1; in comphy_pcie_power_up()
91 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_pcie_power_up()
92 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_pcie_power_up()
100 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up()
102 * U-Boot to mainline version. in comphy_pcie_power_up()
104 * SerDes Lane 4/5 got the PCIe ref-clock #1, in comphy_pcie_power_up()
105 * and SerDes Lane 0 got PCIe ref-clock #0 in comphy_pcie_power_up()
112 if (lane == 0) { in comphy_pcie_power_up()
125 * If PCIe clock is output and clock source from SerDes lane 5, in comphy_pcie_power_up()
126 * we need to configure the clock-source MUX. in comphy_pcie_power_up()
127 * By default, the clock source is from lane 4 in comphy_pcie_power_up()
129 if (pcie_clk && clk_src && (lane == 5)) { in comphy_pcie_power_up()
135 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_pcie_power_up()
136 /* RFU configurations - hard reset comphy */ in comphy_pcie_power_up()
156 /* Wait 1ms - until band gap and ref clock ready */ in comphy_pcie_power_up()
157 mdelay(1); in comphy_pcie_power_up()
176 if (pcie_width != 1) { in comphy_pcie_power_up()
184 /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ in comphy_pcie_power_up()
187 if (pcie_width != 1) { in comphy_pcie_power_up()
191 if (lane == 0) { in comphy_pcie_power_up()
194 } else if (lane == (pcie_width - 1)) { in comphy_pcie_power_up()
207 /* TODO: check if pcie clock is output/input - for bringup use input*/ in comphy_pcie_power_up()
211 /* Only if clock is output, configure the clock-source mux */ in comphy_pcie_power_up()
226 /* Set reference clock comes from group 1 */ in comphy_pcie_power_up()
238 /* Set reference frequcency select - 0x2 for 25MHz*/ in comphy_pcie_power_up()
242 /* Set reference frequcency select - 0x0 for 100MHz*/ in comphy_pcie_power_up()
252 if (pcie_width != 1) { in comphy_pcie_power_up()
259 * Set the amount of time spent in the LoZ state - set for 0x7 only if in comphy_pcie_power_up()
406 /* Genration 2 setting 1*/ in comphy_pcie_power_up()
430 /* Set PLL Charge-pump Current Control */ in comphy_pcie_power_up()
435 /* Set lane rqualization remote setting */ in comphy_pcie_power_up()
454 * For PCIe by4 or by2 - release from reset only after finish to in comphy_pcie_power_up()
457 if ((pcie_width == 1) || (lane == (pcie_width - 1))) { in comphy_pcie_power_up()
460 if (pcie_width != 1) { in comphy_pcie_power_up()
471 * for PCIe by4 or by2 - release from soft reset in comphy_pcie_power_up()
472 * all lanes - can't use read modify write in comphy_pcie_power_up()
477 start_lane = lane; in comphy_pcie_power_up()
478 end_lane = lane + 1; in comphy_pcie_power_up()
482 * for PCIe by4 or by2 - release from soft reset in comphy_pcie_power_up()
491 if (pcie_width != 1) { in comphy_pcie_power_up()
500 /* Read lane status */ in comphy_pcie_power_up()
508 debug("Read from reg = %p - value = 0x%x\n", in comphy_pcie_power_up()
521 static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, in comphy_usb3_power_up() argument
524 u32 mask, data, ret = 1; in comphy_usb3_power_up()
525 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_usb3_power_up()
526 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_usb3_power_up()
530 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_usb3_power_up()
531 /* RFU configurations - hard reset comphy */ in comphy_usb3_power_up()
551 /* Wait 1ms - until band gap and ref clock ready */ in comphy_usb3_power_up()
552 mdelay(1); in comphy_usb3_power_up()
573 /* Set reference clock to come from group 1 - 25Mhz */ in comphy_usb3_power_up()
577 /* Set reference frequcency select - 0x2 */ in comphy_usb3_power_up()
580 /* Set PHY mode to USB - 0x5 */ in comphy_usb3_power_up()
584 /* Set the amount of time spent in the LoZ state - set for 0x7 */ in comphy_usb3_power_up()
588 /* Set max PHY generation setting - 5Gbps */ in comphy_usb3_power_up()
596 /* select de-emphasize 3.5db */ in comphy_usb3_power_up()
607 /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ in comphy_usb3_power_up()
625 /* wait 15ms - for comphy calibration done */ in comphy_usb3_power_up()
627 /* Read lane status */ in comphy_usb3_power_up()
633 debug("Read from reg = %p - value = 0x%x\n", in comphy_usb3_power_up()
643 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, in comphy_sata_power_up() argument
647 u32 mask, data, i, ret = 1; in comphy_sata_power_up()
648 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_sata_power_up()
649 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); in comphy_sata_power_up()
650 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_sata_power_up()
653 int sata_node = -1; /* Set to -1 in order to read the first sata node */ in comphy_sata_power_up()
658 * Assumption - each CP has only one SATA controller in comphy_sata_power_up()
659 * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 in comphy_sata_power_up()
664 for (i = 0; i < (cp_index + 1); i++) in comphy_sata_power_up()
666 gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); in comphy_sata_power_up()
674 gd->fdt_blob, sata_node, "reg", 0, NULL, true); in comphy_sata_power_up()
682 debug("stage: MAC configuration - power down comphy\n"); in comphy_sata_power_up()
693 /* SATA 1 power down */ in comphy_sata_power_up()
699 /* SATA port 1 disable */ in comphy_sata_power_up()
704 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_sata_power_up()
705 /* RFU configurations - hard reset comphy */ in comphy_sata_power_up()
716 /* Set select data width 40Bit - SATA mode only */ in comphy_sata_power_up()
728 /* Wait 1ms - until band gap and ref clock ready */ in comphy_sata_power_up()
729 mdelay(1); in comphy_sata_power_up()
733 /* Set reference clock to comes from group 1 - choose 25Mhz */ in comphy_sata_power_up()
737 /* Reference frequency select set 1 (for SATA = 25Mhz) */ in comphy_sata_power_up()
744 /* Set max PHY generation setting - 6Gbps */ in comphy_sata_power_up()
844 /* DFE F3-F5 Coefficient Control */ in comphy_sata_power_up()
935 data |= (1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET); in comphy_sata_power_up()
939 data |= (1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET); in comphy_sata_power_up()
954 * MAC configuration power up comphy - power up PLL/TX/RX in comphy_sata_power_up()
963 /* SATA 1 power up */ in comphy_sata_power_up()
969 /* SATA port 1 enable */ in comphy_sata_power_up()
990 debug("Read from reg = %p - value = 0x%x\n", in comphy_sata_power_up()
1002 static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, in comphy_sgmii_power_up() argument
1006 u32 mask, data, ret = 1; in comphy_sgmii_power_up()
1007 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_sgmii_power_up()
1008 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); in comphy_sgmii_power_up()
1009 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_sgmii_power_up()
1013 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_sgmii_power_up()
1014 /* RFU configurations - hard reset comphy */ in comphy_sgmii_power_up()
1039 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in comphy_sgmii_power_up()
1059 /* Wait 1ms - until band gap and ref clock ready */ in comphy_sgmii_power_up()
1060 mdelay(1); in comphy_sgmii_power_up()
1078 /* rx control 1 */ in comphy_sgmii_power_up()
1089 /* Set analog paramters from ETP(HW) - for now use the default datas */ in comphy_sgmii_power_up()
1096 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); in comphy_sgmii_power_up()
1113 debug("Read from reg = %p - value = 0x%x\n", in comphy_sgmii_power_up()
1132 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sgmii_power_up()
1149 static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, in comphy_sfi_power_up() argument
1152 u32 mask, data, ret = 1; in comphy_sfi_power_up()
1153 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_sfi_power_up()
1154 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); in comphy_sfi_power_up()
1155 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_sfi_power_up()
1159 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_sfi_power_up()
1160 /* RFU configurations - hard reset comphy */ in comphy_sfi_power_up()
1198 /* Wait 1ms - until band gap and ref clock ready */ in comphy_sfi_power_up()
1199 mdelay(1); in comphy_sfi_power_up()
1221 /* rx control 1 */ in comphy_sfi_power_up()
1235 data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; in comphy_sfi_power_up()
1237 data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1239 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; in comphy_sfi_power_up()
1241 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1254 /* 0x7-DFE Resolution control */ in comphy_sfi_power_up()
1258 /* 0xd-G1_Setting_0 */ in comphy_sfi_power_up()
1269 /* Genration 1 setting 2 (G1_Setting_2) */ in comphy_sfi_power_up()
1287 /* Generation 1 Setting 5 (g1_setting_5) */ in comphy_sfi_power_up()
1291 /* 0xE-G1_Setting_1 */ in comphy_sfi_power_up()
1313 /* 0xA-DFE_Reg3 */ in comphy_sfi_power_up()
1320 /* 0x111-G1_Setting_4 */ in comphy_sfi_power_up()
1324 /* Genration 1 setting 3 (G1_Setting_3) */ in comphy_sfi_power_up()
1395 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); in comphy_sfi_power_up()
1413 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sfi_power_up()
1432 debug("Read from reg = %p - value = 0x%x\n", in comphy_sfi_power_up()
1450 static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base, in comphy_rxauii_power_up() argument
1453 u32 mask, data, ret = 1; in comphy_rxauii_power_up()
1454 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_rxauii_power_up()
1455 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); in comphy_rxauii_power_up()
1456 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_rxauii_power_up()
1460 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_rxauii_power_up()
1461 /* RFU configurations - hard reset comphy */ in comphy_rxauii_power_up()
1468 if (lane == 2) { in comphy_rxauii_power_up()
1473 if (lane == 4) { in comphy_rxauii_power_up()
1511 /* Wait 1ms - until band gap and ref clock ready */ in comphy_rxauii_power_up()
1512 mdelay(1); in comphy_rxauii_power_up()
1529 /* rx control 1 */ in comphy_rxauii_power_up()
1546 /* 0x7-DFE Resolution control */ in comphy_rxauii_power_up()
1549 /* 0xd-G1_Setting_0 */ in comphy_rxauii_power_up()
1553 /* 0xE-G1_Setting_1 */ in comphy_rxauii_power_up()
1561 /* 0xA-DFE_Reg3 */ in comphy_rxauii_power_up()
1568 /* 0x111-G1_Setting_4 */ in comphy_rxauii_power_up()
1573 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); in comphy_rxauii_power_up()
1591 debug("Read from reg = %p - value = 0x%x\n", in comphy_rxauii_power_up()
1610 debug("Read from reg = %p - value = 0x%x\n", in comphy_rxauii_power_up()
1636 debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", in comphy_utmi_power_down()
1647 debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", in comphy_utmi_power_down()
1667 mdelay(1); in comphy_utmi_power_down()
1685 /* Feedback Clock Divider Select - 90 for 25Mhz*/ in comphy_utmi_phy_config()
1688 /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ in comphy_utmi_phy_config()
1722 /* Set Control VDAT Reference Voltage - 0.325V */ in comphy_utmi_phy_config()
1725 /* Set Control VSRC Reference Voltage - 0.6V */ in comphy_utmi_phy_config()
1738 u32 data, mask, ret = 1; in comphy_utmi_power_up()
1742 debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", in comphy_utmi_power_up()
1759 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1768 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1778 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1794 * 1. Power down transceiver and PLL
1797 * Note: - Power down/up should be once for both UTMI PHYs
1798 * - comphy_dedicated_phys_init call this function if at least there is
1858 * - not muxed SerDes lanes e.g. UTMI PHY
1870 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, in comphy_dedicated_phys_init()
1871 "marvell,mvebu-utmi-2.6.0"); in comphy_dedicated_phys_init()
1878 gd->fdt_blob, node, "reg", 0, NULL, true); in comphy_dedicated_phys_init()
1888 gd->fdt_blob, node, "reg", 1, NULL, true); in comphy_dedicated_phys_init()
1898 gd->fdt_blob, node, "reg", 2, NULL, true); in comphy_dedicated_phys_init()
1910 gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); in comphy_dedicated_phys_init()
1918 gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); in comphy_dedicated_phys_init()
1934 u32 lane, comphy_max_count; in comphy_mux_cp110_init() local
1936 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; in comphy_mux_cp110_init()
1937 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; in comphy_mux_cp110_init()
1941 * the comphy_mux_init modify the type of the lane if the type in comphy_mux_cp110_init()
1946 for (lane = 0; lane < comphy_max_count; lane++) { in comphy_mux_cp110_init()
1947 comphy_map_pipe_data[lane].type = serdes_map[lane].type; in comphy_mux_cp110_init()
1948 comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; in comphy_mux_cp110_init()
1949 comphy_map_phy_data[lane].type = serdes_map[lane].type; in comphy_mux_cp110_init()
1950 comphy_map_phy_data[lane].speed = serdes_map[lane].speed; in comphy_mux_cp110_init()
1952 ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; in comphy_mux_cp110_init()
1956 ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; in comphy_mux_cp110_init()
1960 for (lane = 0; lane < comphy_max_count; lane++) { in comphy_mux_cp110_init()
1961 if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && in comphy_mux_cp110_init()
1962 (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) in comphy_mux_cp110_init()
1963 serdes_map[lane].type = PHY_TYPE_UNCONNECTED; in comphy_mux_cp110_init()
1972 u32 comphy_max_count, lane, ret = 0; in comphy_cp110_init() local
1977 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; in comphy_cp110_init()
1978 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; in comphy_cp110_init()
1979 hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; in comphy_cp110_init()
1984 /* Check if the first 4 lanes configured as By-4 */ in comphy_cp110_init()
1985 for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; in comphy_cp110_init()
1986 lane++, ptr_comphy_map++) { in comphy_cp110_init()
1987 if (ptr_comphy_map->type != PHY_TYPE_PEX0) in comphy_cp110_init()
1992 for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count; in comphy_cp110_init()
1993 lane++, ptr_comphy_map++) { in comphy_cp110_init()
1994 debug("Initialize serdes number %d\n", lane); in comphy_cp110_init()
1995 debug("Serdes type = 0x%x\n", ptr_comphy_map->type); in comphy_cp110_init()
1996 if (lane == 4) { in comphy_cp110_init()
2001 pcie_width = 1; in comphy_cp110_init()
2003 switch (ptr_comphy_map->type) { in comphy_cp110_init()
2013 lane, pcie_width, ptr_comphy_map->clk_src, in comphy_cp110_init()
2014 serdes_map->end_point, in comphy_cp110_init()
2022 lane, hpipe_base_addr, comphy_base_addr, in comphy_cp110_init()
2023 ptr_chip_cfg->cp_index, in comphy_cp110_init()
2024 serdes_map[lane].invert); in comphy_cp110_init()
2029 ret = comphy_usb3_power_up(lane, hpipe_base_addr, in comphy_cp110_init()
2036 if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { in comphy_cp110_init()
2037 debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", in comphy_cp110_init()
2038 lane); in comphy_cp110_init()
2039 ptr_comphy_map->speed = PHY_SPEED_1_25G; in comphy_cp110_init()
2042 lane, ptr_comphy_map->speed, hpipe_base_addr, in comphy_cp110_init()
2046 ret = comphy_sfi_power_up(lane, hpipe_base_addr, in comphy_cp110_init()
2048 ptr_comphy_map->speed); in comphy_cp110_init()
2052 ret = comphy_rxauii_power_up(lane, hpipe_base_addr, in comphy_cp110_init()
2057 lane); in comphy_cp110_init()
2062 * If interface wans't initialized, set the lane to in comphy_cp110_init()
2065 ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; in comphy_cp110_init()
2066 pr_err("PLL is not locked - Failed to initialize lane %d\n", in comphy_cp110_init()
2067 lane); in comphy_cp110_init()