Lines Matching +full:1 +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
17 /* Lane 0 */
27 /* Lane 1 */
36 /* Lane 2 */
66 /* 0 1 2 3 4 5 6 7 */
67 /*-----------------------------------------------------------*/
121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
123 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
124 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
125 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
126 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
127 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
128 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
129 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
130 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
131 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
132 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
138 * return: 1 on success, 0 on timeout
144 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { in comphy_poll_reg()
151 return 1; in comphy_poll_reg()
163 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
172 * 1. Enable max PLL. in comphy_pcie_power_up()
272 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
286 * 1. Select 40-bit data width width in comphy_sata_power_up()
312 * 5. Set vendor-specific configuration (??) in comphy_sata_power_up()
339 static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane) in usb3_reg_set16() argument
342 * When Lane 2 PHY is for USB3, access the PHY registers in usb3_reg_set16()
345 * within the SATA Host Controller registers, Lane 2 base register in usb3_reg_set16()
349 if (lane == 2) in usb3_reg_set16()
359 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
361 static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) in comphy_usb3_power_up() argument
368 * 1. Power up OTG module in comphy_usb3_power_up()
380 /* set PRD_TXDEEMPH (3.5db de-emph) */ in comphy_usb3_power_up()
381 usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane); in comphy_usb3_power_up()
387 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db in comphy_usb3_power_up()
395 | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane); in comphy_usb3_power_up()
398 usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane); in comphy_usb3_power_up()
402 * from lane configuration in comphy_usb3_power_up()
404 usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane); in comphy_usb3_power_up()
406 /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ in comphy_usb3_power_up()
408 usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane); in comphy_usb3_power_up()
411 usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane); in comphy_usb3_power_up()
417 usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF, lane); in comphy_usb3_power_up()
426 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane); in comphy_usb3_power_up()
427 usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane); in comphy_usb3_power_up()
430 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane); in comphy_usb3_power_up()
431 usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane); in comphy_usb3_power_up()
437 usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF, lane); in comphy_usb3_power_up()
442 usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF, lane); in comphy_usb3_power_up()
445 * 7. Set 20-bit data width in comphy_usb3_power_up()
447 usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF, lane); in comphy_usb3_power_up()
453 lane); in comphy_usb3_power_up()
459 usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane); in comphy_usb3_power_up()
462 usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane); in comphy_usb3_power_up()
467 usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00, lane); in comphy_usb3_power_up()
472 usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF, lane); in comphy_usb3_power_up()
479 | 0x20, 0xFFFF, lane); in comphy_usb3_power_up()
485 if (lane == 2) { in comphy_usb3_power_up()
530 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
538 if (usb32 != 0 && usb32 != 1) { in comphy_usb2_power_up()
539 printf("invalid usb32 value: (%d), should be either 0 or 1\n", in comphy_usb2_power_up()
555 * 1. PHY pull up and disable USB2 suspend in comphy_usb2_power_up()
615 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
622 * 1. Bus power ON, Bus voltage 1.8V in comphy_emmc_power_up()
632 * 3. Set Capabilities 1_2 in comphy_emmc_power_up()
655 return 1; in comphy_emmc_power_up()
663 static void comphy_sgmii_phy_init(u32 lane, u32 speed) in comphy_sgmii_phy_init() argument
688 reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF); in comphy_sgmii_phy_init()
695 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
697 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) in comphy_sgmii_power_up() argument
705 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 in comphy_sgmii_power_up()
711 * 2. Reset PHY by setting PHY input port PIN_RESET=1. in comphy_sgmii_power_up()
712 * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep in comphy_sgmii_power_up()
716 reg_set(COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
724 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy); in comphy_sgmii_power_up()
731 reg_set(COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
737 reg_set(COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
747 * 8. Wait 1mS for bandgap and reference clocks to stabilize; in comphy_sgmii_power_up()
753 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), in comphy_sgmii_power_up()
760 reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel); in comphy_sgmii_power_up()
767 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), in comphy_sgmii_power_up()
771 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), in comphy_sgmii_power_up()
775 /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */ in comphy_sgmii_power_up()
788 reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask); in comphy_sgmii_power_up()
805 * group to get the related GEN table during real chip bring-up. in comphy_sgmii_power_up()
811 debug("Running C-DPI phy init %s mode\n", in comphy_sgmii_power_up()
812 speed == PHY_SPEED_3_125G ? "2G5" : "1G"); in comphy_sgmii_power_up()
814 comphy_sgmii_phy_init(lane, speed); in comphy_sgmii_power_up()
819 * (R02h[9]) to 1 to shorten COMPHY simulation time. in comphy_sgmii_power_up()
823 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX in comphy_sgmii_power_up()
831 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0); in comphy_sgmii_power_up()
834 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0); in comphy_sgmii_power_up()
837 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 in comphy_sgmii_power_up()
839 * programming should be done before PIN_PU_PLL=1. There should be in comphy_sgmii_power_up()
842 reg_set(COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
848 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. in comphy_sgmii_power_up()
850 ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */ in comphy_sgmii_power_up()
855 printf("Failed to lock PLL for SGMII PHY %d\n", lane); in comphy_sgmii_power_up()
860 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle); in comphy_sgmii_power_up()
863 * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. in comphy_sgmii_power_up()
866 * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after in comphy_sgmii_power_up()
867 * PIN_RX_INIT_DONE= 1. in comphy_sgmii_power_up()
870 reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0); in comphy_sgmii_power_up()
872 ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */ in comphy_sgmii_power_up()
877 printf("Failed to init RX of SGMII PHY %d\n", lane); in comphy_sgmii_power_up()
891 int node, usb32, ret = 1; in comphy_dedicated_phys_init()
892 const void *blob = gd->fdt_blob; in comphy_dedicated_phys_init()
896 for (usb32 = 0; usb32 <= 1; usb32++) { in comphy_dedicated_phys_init()
903 blob, -1, "marvell,armada3700-ehci"); in comphy_dedicated_phys_init()
906 blob, -1, "marvell,armada3700-xhci"); in comphy_dedicated_phys_init()
925 node = fdt_node_offset_by_compatible(blob, -1, in comphy_dedicated_phys_init()
926 "marvell,armada-3700-ahci"); in comphy_dedicated_phys_init()
941 node = fdt_node_offset_by_compatible(blob, -1, in comphy_dedicated_phys_init()
942 "marvell,armada-8k-sdhci"); in comphy_dedicated_phys_init()
945 blob, -1, "marvell,armada-3700-sdhci"); in comphy_dedicated_phys_init()
969 u32 comphy_max_count = chip_cfg->comphy_lanes_count; in comphy_a3700_init()
970 u32 lane, ret = 0; in comphy_a3700_init() local
975 chip_cfg->mux_data = a3700_comphy_mux_data; in comphy_a3700_init()
978 for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count; in comphy_a3700_init()
979 lane++, comphy_map++) { in comphy_a3700_init()
980 debug("Initialize serdes number %d\n", lane); in comphy_a3700_init()
982 comphy_map->type, comphy_map->invert); in comphy_a3700_init()
984 switch (comphy_map->type) { in comphy_a3700_init()
990 ret = comphy_pcie_power_up(comphy_map->speed, in comphy_a3700_init()
991 comphy_map->invert); in comphy_a3700_init()
996 ret = comphy_usb3_power_up(lane, in comphy_a3700_init()
997 comphy_map->type, in comphy_a3700_init()
998 comphy_map->speed, in comphy_a3700_init()
999 comphy_map->invert); in comphy_a3700_init()
1004 ret = comphy_sgmii_power_up(lane, comphy_map->speed, in comphy_a3700_init()
1005 comphy_map->invert); in comphy_a3700_init()
1010 lane); in comphy_a3700_init()
1011 ret = 1; in comphy_a3700_init()
1015 printf("PLL is not locked - Failed to initialize lane %d\n", in comphy_a3700_init()
1016 lane); in comphy_a3700_init()