ram/stm32mp1/stm32mp1_ddr_regs.h

1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
13 	u8 reserved008[0x10 - 0x8];
15 	u32 mrctrl1;		/* 0x14 Control 1*/
20 	u8 reserved028[0x30 - 0x28];
24 	u8 reserved03c[0x50 - 0x3C];
26 	u32 reserved054;	/* 0x54 Refresh Control 1*/
31 	u8 reserved068[0xc0 - 0x68];
37 	u32 init1;		/* 0xd4 SDRAM Initialization 1*/
45 	u8 reserved0f4[0x100 - 0xf4];
47 	u32 dramtmg1;		/* 0x104 SDRAM Timing 1*/
55 	u8 reserved124[0x138 - 0x124];
58 	u8 reserved140[0x180 - 0x140];
60 	u32 zqctl1;		/* 0x184 ZQ Control 1*/
64 	u32 dfitmg1;		/* 0x194 DFI Timing 1*/
68 	u32 dfiupd1;		/* 0x1a4 DFI Update 1*/
72 	u8 reserved1b4[0x1bc - 0x1b4];
74 	u8 reserved1c0[0x1c4 - 0x1c0];
76 	u8 reserved1c8[0x204 - 0x1c8];
77 	u32 addrmap1;		/* 0x204 Address Map 1*/
83 	u8 reserved21c[0x224 - 0x21c];
87 	u8 reserved230[0x240 - 0x230];
90 	u8 reserved248[0x250 - 0x248];
92 	u32 sched1;		/* 0x254 Scheduler Control 1*/
94 	u32 perfhpr1;		/* 0x25c High Priority Read CAM 1*/
96 	u32 perflpr1;		/* 0x264 Low Priority Read CAM 1*/
98 	u32 perfwr1;		/* 0x26c Write CAM 1*/
99 	u8 reserved27c[0x300 - 0x270];
101 	u32 dbg1;		/* 0x304 Debug 1*/
105 	u8 reserved314[0x320 - 0x314];
108 	u8 reserved328[0x36c - 0x328];
111 	u8 reserved374[0x3fc - 0x374];
120 	u8 reserved40c[0x490 - 0x40c];
123 	u32 pcfgqos1_0;		/* 0x498 Read QoS Configuration 1*/
125 	u32 pcfgwqos1_0;	/* 0x4a0 Write QoS Configuration 1*/
126 	u8 reserved4a4[0x4b4 - 0x4a4];
128 	/* PORT 1 */
131 	u8 reserved4bc[0x540 - 0x4bc];
134 	u32 pcfgqos1_1;		/* 0x548 Read QoS Configuration 1*/
136 	u32 pcfgwqos1_1;	/* 0x550 Write QoS Configuration 1*/
148 	u32 ptr1;		/* 0x1C R/W PHY Timing 1*/
158 	u32 mr1;		/* 0x44 Mode 1*/
165 	u8 res1[0x0c0 - 0x060];	/* 0x60 */
173 	u32 dcusr1;		/* 0xdc DCU Status 1*/
174 	u8 res2[0x100 - 0xe0];	/* 0xe0 */
181 	u32 bistar1;		/* 0x118 BIST Address 1*/
187 	u32 bistber1;		/* 0x130 BIST Bit Error 1*/
191 	u32 bistfwr1;		/* 0x140 BIST Fail Word 1*/
192 	u8 res3[0x178 - 0x144];	/* 0x144 */
194 	u32 gpr1;		/* 0x17C General Purpose 1 (GPR1)*/
196 	u32 zq0cr1;		/* 0x184 zq 0 control 1 */
198 	u32 zq0sr1;		/* 0x18C zq 0 status 1 */
199 	u8 res4[0x1C0 - 0x190];	/* 0x190 */
200 	u32 dx0gcr;		/* 0x1c0 Byte lane 0 General Configuration*/
201 	u32 dx0gsr0;		/* 0x1c4 Byte lane 0 General Status 0*/
202 	u32 dx0gsr1;		/* 0x1c8 Byte lane 0 General Status 1*/
203 	u32 dx0dllcr;		/* 0x1cc Byte lane 0 DLL Control*/
204 	u32 dx0dqtr;		/* 0x1d0 Byte lane 0 DQ Timing*/
205 	u32 dx0dqstr;		/* 0x1d4 Byte lane 0 DQS Timing*/
206 	u8 res5[0x200 - 0x1d8];	/* 0x1d8 */
207 	u32 dx1gcr;		/* 0x200 Byte lane 1 General Configuration*/
208 	u32 dx1gsr0;		/* 0x204 Byte lane 1 General Status 0*/
209 	u32 dx1gsr1;		/* 0x208 Byte lane 1 General Status 1*/
210 	u32 dx1dllcr;		/* 0x20c Byte lane 1 DLL Control*/
211 	u32 dx1dqtr;		/* 0x210 Byte lane 1 DQ Timing*/
212 	u32 dx1dqstr;		/* 0x214 Byte lane 1 QS Timing*/
213 	u8 res6[0x240 - 0x218];	/* 0x218 */
214 	u32 dx2gcr;		/* 0x240 Byte lane 2 General Configuration*/
215 	u32 dx2gsr0;		/* 0x244 Byte lane 2 General Status 0*/
216 	u32 dx2gsr1;		/* 0x248 Byte lane 2 General Status 1*/
217 	u32 dx2dllcr;		/* 0x24c Byte lane 2 DLL Control*/
218 	u32 dx2dqtr;		/* 0x250 Byte lane 2 DQ Timing*/
219 	u32 dx2dqstr;		/* 0x254 Byte lane 2 QS Timing*/
220 	u8 res7[0x280 - 0x258];	/* 0x258 */
221 	u32 dx3gcr;		/* 0x280 Byte lane 3 General Configuration*/
222 	u32 dx3gsr0;		/* 0x284 Byte lane 3 General Status 0*/
223 	u32 dx3gsr1;		/* 0x288 Byte lane 3 General Status 1*/
224 	u32 dx3dllcr;		/* 0x28c Byte lane 3 DLL Control*/
225 	u32 dx3dqtr;		/* 0x290 Byte lane 3 DQ Timing*/
226 	u32 dx3dqstr;		/* 0x294 Byte lane 3 QS Timing*/
239 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF	(1 << 12)
244 #define DDRCTRL_STAT_OPERATING_MODE_NORMAL	1
261 #define DDRCTRL_PWRCTL_POWERDOWN_EN		BIT(1)
274 #define DDRCTRL_DBG1_DIS_HIF			BIT(1)
301 #define DDRPHYC_PIR_DLLSRST			BIT(1)
339 #define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK		GENMASK(1, 0)