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/openbmc/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpkg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
16 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
21 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
26 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
33 DPKG_FROM_FIELD = 1,
38 * enum dpkg_extract_type - Enumeration for selecting extraction type
41 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
47 DPKG_EXTRACT_FROM_DATA = 1,
52 * struct dpkg_mask - A structure for defining a single extraction mask
[all …]
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
[all …]
H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
[all …]
/openbmc/linux/drivers/net/dsa/microchip/
H A Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2024 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define PME_ENABLE BIT(1)
44 #define PME_POLARITY BIT(0)
48 #define SW_GIGABIT_ABLE BIT(6)
49 #define SW_REDUNDANCY_ABLE BIT(5)
50 #define SW_AVB_ABLE BIT(4)
68 #define SW_QW_ABLE BIT(5)
74 #define LUE_INT BIT(31)
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H A Dlan937x_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
8 #define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
10 /* 0 - Operation */
13 #define SW_PHY_REG_BLOCK BIT(7)
14 #define SW_FAST_MODE BIT(3)
15 #define SW_FAST_MODE_OVERRIDE BIT(2)
20 #define LUE_INT BIT(31)
21 #define TRIG_TS_INT BIT(30)
22 #define APB_TIMEOUT_INT BIT(29)
[all …]
H A Dksz8795_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
18 #define SW_REVISION_S 1
22 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
23 #define KSZ8863_PCS_RESET BIT(0)
27 #define SW_NEW_BACKOFF BIT(7)
28 #define SW_GLOBAL_RESET BIT(6)
29 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
30 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
31 #define SW_LINK_AUTO_AGING BIT(0)
35 #define SW_HUGE_PACKET BIT(6)
[all …]
/openbmc/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
16 #define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
137 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
[all …]
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_device.c1 // SPDX-License-Identifier: MIT
34 /* ICL DSI 0 and 1 */
174 .has_overlay = 1, \
175 .cursor_needs_physical = 1, \
176 .overlay_needs_physical = 1, \
177 .has_gmch = 1, \
183 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
185 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
188 .has_overlay = 1, \
189 .overlay_needs_physical = 1, \
[all …]
/openbmc/linux/drivers/net/wireless/ath/wil6210/
H A Dtxrx.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
13 #define BUF_SW_OWNED (1)
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
[all …]
H A Dtxrx_edma.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016,2018-2019, The Linux Foundation. All rights reserved.
22 #define WIL_TX_STATUS_IRQ_IDX 1
28 #define WIL_EDMA_TIME_UNIT_CLK_CYCLES (330) /* fits 1 usec */
31 #define WIL_RX_EDMA_ERROR_MIC (1)
37 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1))
38 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1))
40 #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11)
49 #define WIL_RX_EDMA_MID_VALID_BIT BIT(20)
55 #define WIL_EDMA_DESC_TX_CFG_EOP_LEN 1
[all …]
/openbmc/u-boot/drivers/sound/
H A Dmax98090.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * max98090.h -- MAX98090 ALSA SoC Audio driver
63 #define M98090_REG_CNT (0xff + 1)
66 /* MAX98090 Registers Bit Fields */
71 #define M98090_SWRESET_MASK BIT(7)
76 #define M98090_SR_96K_MASK BIT(5)
78 #define M98090_SR_96K_WIDTH 1
79 #define M98090_SR_32K_MASK BIT(4)
81 #define M98090_SR_32K_WIDTH 1
82 #define M98090_SR_48K_MASK BIT(3)
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
19 * Default 1.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
[all …]
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/gpio/phosphor-gpio-monitor/
H A Dmulti-gpios-sys-init3 # shellcheck source=meta-facebook/recipes-fb/obmc_functions/files/fb-common-functions
4 source /usr/libexec/fb-common-functions
5 # shellcheck source=meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/power-cmd
6 source /usr/libexec/phosphor-state-manager/power-cmd
12 if [ "$(get_gpio "power-host-good")" -eq 1 ] && [ "$valid_sgpio" -eq 0 ]; then
13 systemctl start obmc-led-group-start@power_on.service
15 systemctl start obmc-led-group-stop@power_on.service
20 if [ "$(get_gpio post-end-n)" -eq 0 ]; then
21 busctl set-property xyz.openbmc_project.State.Host0 /xyz/openbmc_project/state/host0 \
25 busctl set-property xyz.openbmc_project.Software.Manager \
[all …]
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_drv.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
31 /* -----------------------------------------------------------------------------
41 .channels_mask = BIT(1) | BIT(0),
47 .possible_crtcs = BIT(1) | BIT(0),
51 .possible_crtcs = BIT(0),
52 .port = 1,
55 .num_lvds = 1,
[all …]
/openbmc/linux/drivers/net/ethernet/cortina/
H A Dgemini.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
57 #define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
91 /* GMAC 0/1 DMA/TOE register */
148 /* TOE GMAC 0/1 register */
[all …]
/openbmc/linux/drivers/staging/emxx_udc/
H A Demxx_udc.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /*---------------------------------------------------------------------------*/
13 /*----------------- Default define */
14 #define USE_DMA 1
15 #define USE_SUSPEND_WAIT 1
17 /*------------ Board dependence(Resource) */
24 /*------------ Board dependence(Wait) */
27 #define VBUS_CHATTERING_MDELAY 1
31 /*------------ Controller dependence */
36 #define EPC_RST_DISABLE_TIME 1 /* 1 usec */
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
44 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Bit 7 RW Reserved. Default 1.
13 * Bit 6 RW Reserved. Default 1.
14 * Bit 5 RW Reserved. Default 1.
15 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
16 * Default 1.
17 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
19 * Default 1.
20 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
21 * Default 1.
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
H A Dplx9080.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
40 * terminal count" bit, and a data transfer direction.
50 * Register Offsets and Bit Definitions
55 /* Local Address Space 1 Range Register */
58 #define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
59 #define PLX_LASRR_MLOC_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dreset_manager_arria10.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2016-2017 Intel Corporation
9 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
55 * 1 ... per0modrst
60 #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
61 #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
62 #define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
63 #define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
64 #define RSTMGR_QSPI RSTMGR_DEFINE(1, 6)
65 #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dtda1997x_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
128 #define DETECT_UTIL BIT(7) /* utility of HDMI level */
129 #define DETECT_HPD BIT(6) /* HPD of HDMI level */
130 #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */
131 #define DETECT_5V_B BIT(1) /* 5V present on input B */
132 #define DETECT_5V_A BIT(0) /* 5V present on input A */
135 #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
136 #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */
137 #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
[all …]

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