159d8bf5dSNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 29ac0038dSTim Harvey /* 39ac0038dSTim Harvey * Copyright (C) 2018 Gateworks Corporation 49ac0038dSTim Harvey */ 59ac0038dSTim Harvey 69ac0038dSTim Harvey /* Page 0x00 - General Control */ 79ac0038dSTim Harvey #define REG_VERSION 0x0000 89ac0038dSTim Harvey #define REG_INPUT_SEL 0x0001 99ac0038dSTim Harvey #define REG_SVC_MODE 0x0002 109ac0038dSTim Harvey #define REG_HPD_MAN_CTRL 0x0003 119ac0038dSTim Harvey #define REG_RT_MAN_CTRL 0x0004 129ac0038dSTim Harvey #define REG_STANDBY_SOFT_RST 0x000A 139ac0038dSTim Harvey #define REG_HDMI_SOFT_RST 0x000B 149ac0038dSTim Harvey #define REG_HDMI_INFO_RST 0x000C 159ac0038dSTim Harvey #define REG_INT_FLG_CLR_TOP 0x000E 169ac0038dSTim Harvey #define REG_INT_FLG_CLR_SUS 0x000F 179ac0038dSTim Harvey #define REG_INT_FLG_CLR_DDC 0x0010 189ac0038dSTim Harvey #define REG_INT_FLG_CLR_RATE 0x0011 199ac0038dSTim Harvey #define REG_INT_FLG_CLR_MODE 0x0012 209ac0038dSTim Harvey #define REG_INT_FLG_CLR_INFO 0x0013 219ac0038dSTim Harvey #define REG_INT_FLG_CLR_AUDIO 0x0014 229ac0038dSTim Harvey #define REG_INT_FLG_CLR_HDCP 0x0015 239ac0038dSTim Harvey #define REG_INT_FLG_CLR_AFE 0x0016 249ac0038dSTim Harvey #define REG_INT_MASK_TOP 0x0017 259ac0038dSTim Harvey #define REG_INT_MASK_SUS 0x0018 269ac0038dSTim Harvey #define REG_INT_MASK_DDC 0x0019 279ac0038dSTim Harvey #define REG_INT_MASK_RATE 0x001A 289ac0038dSTim Harvey #define REG_INT_MASK_MODE 0x001B 299ac0038dSTim Harvey #define REG_INT_MASK_INFO 0x001C 309ac0038dSTim Harvey #define REG_INT_MASK_AUDIO 0x001D 319ac0038dSTim Harvey #define REG_INT_MASK_HDCP 0x001E 329ac0038dSTim Harvey #define REG_INT_MASK_AFE 0x001F 339ac0038dSTim Harvey #define REG_DETECT_5V 0x0020 349ac0038dSTim Harvey #define REG_SUS_STATUS 0x0021 359ac0038dSTim Harvey #define REG_V_PER 0x0022 369ac0038dSTim Harvey #define REG_H_PER 0x0025 379ac0038dSTim Harvey #define REG_HS_WIDTH 0x0027 389ac0038dSTim Harvey #define REG_FMT_H_TOT 0x0029 399ac0038dSTim Harvey #define REG_FMT_H_ACT 0x002b 409ac0038dSTim Harvey #define REG_FMT_H_FRONT 0x002d 419ac0038dSTim Harvey #define REG_FMT_H_SYNC 0x002f 429ac0038dSTim Harvey #define REG_FMT_H_BACK 0x0031 439ac0038dSTim Harvey #define REG_FMT_V_TOT 0x0033 449ac0038dSTim Harvey #define REG_FMT_V_ACT 0x0035 459ac0038dSTim Harvey #define REG_FMT_V_FRONT_F1 0x0037 469ac0038dSTim Harvey #define REG_FMT_V_FRONT_F2 0x0038 479ac0038dSTim Harvey #define REG_FMT_V_SYNC 0x0039 489ac0038dSTim Harvey #define REG_FMT_V_BACK_F1 0x003a 499ac0038dSTim Harvey #define REG_FMT_V_BACK_F2 0x003b 509ac0038dSTim Harvey #define REG_FMT_DE_ACT 0x003c 519ac0038dSTim Harvey #define REG_RATE_CTRL 0x0040 529ac0038dSTim Harvey #define REG_CLK_MIN_RATE 0x0043 539ac0038dSTim Harvey #define REG_CLK_MAX_RATE 0x0046 549ac0038dSTim Harvey #define REG_CLK_A_STATUS 0x0049 559ac0038dSTim Harvey #define REG_CLK_A_RATE 0x004A 569ac0038dSTim Harvey #define REG_DRIFT_CLK_A_REG 0x004D 579ac0038dSTim Harvey #define REG_CLK_B_STATUS 0x004E 589ac0038dSTim Harvey #define REG_CLK_B_RATE 0x004F 599ac0038dSTim Harvey #define REG_DRIFT_CLK_B_REG 0x0052 609ac0038dSTim Harvey #define REG_HDCP_CTRL 0x0060 619ac0038dSTim Harvey #define REG_HDCP_KDS 0x0061 629ac0038dSTim Harvey #define REG_HDCP_BCAPS 0x0063 639ac0038dSTim Harvey #define REG_HDCP_KEY_CTRL 0x0064 649ac0038dSTim Harvey #define REG_INFO_CTRL 0x0076 659ac0038dSTim Harvey #define REG_INFO_EXCEED 0x0077 669ac0038dSTim Harvey #define REG_PIX_REPEAT 0x007B 679ac0038dSTim Harvey #define REG_AUDIO_PATH 0x007C 689ac0038dSTim Harvey #define REG_AUDCFG 0x007D 699ac0038dSTim Harvey #define REG_AUDIO_OUT_ENABLE 0x007E 709ac0038dSTim Harvey #define REG_AUDIO_OUT_HIZ 0x007F 719ac0038dSTim Harvey #define REG_VDP_CTRL 0x0080 729ac0038dSTim Harvey #define REG_VDP_MATRIX 0x0081 739ac0038dSTim Harvey #define REG_VHREF_CTRL 0x00A0 749ac0038dSTim Harvey #define REG_PXCNT_PR 0x00A2 759ac0038dSTim Harvey #define REG_PXCNT_NPIX 0x00A4 769ac0038dSTim Harvey #define REG_LCNT_PR 0x00A6 779ac0038dSTim Harvey #define REG_LCNT_NLIN 0x00A8 789ac0038dSTim Harvey #define REG_HREF_S 0x00AA 799ac0038dSTim Harvey #define REG_HREF_E 0x00AC 809ac0038dSTim Harvey #define REG_HS_S 0x00AE 819ac0038dSTim Harvey #define REG_HS_E 0x00B0 829ac0038dSTim Harvey #define REG_VREF_F1_S 0x00B2 839ac0038dSTim Harvey #define REG_VREF_F1_WIDTH 0x00B4 849ac0038dSTim Harvey #define REG_VREF_F2_S 0x00B5 859ac0038dSTim Harvey #define REG_VREF_F2_WIDTH 0x00B7 869ac0038dSTim Harvey #define REG_VS_F1_LINE_S 0x00B8 879ac0038dSTim Harvey #define REG_VS_F1_LINE_WIDTH 0x00BA 889ac0038dSTim Harvey #define REG_VS_F2_LINE_S 0x00BB 899ac0038dSTim Harvey #define REG_VS_F2_LINE_WIDTH 0x00BD 909ac0038dSTim Harvey #define REG_VS_F1_PIX_S 0x00BE 919ac0038dSTim Harvey #define REG_VS_F1_PIX_E 0x00C0 929ac0038dSTim Harvey #define REG_VS_F2_PIX_S 0x00C2 939ac0038dSTim Harvey #define REG_VS_F2_PIX_E 0x00C4 949ac0038dSTim Harvey #define REG_FREF_F1_S 0x00C6 959ac0038dSTim Harvey #define REG_FREF_F2_S 0x00C8 969ac0038dSTim Harvey #define REG_FDW_S 0x00ca 979ac0038dSTim Harvey #define REG_FDW_E 0x00cc 989ac0038dSTim Harvey #define REG_BLK_GY 0x00da 999ac0038dSTim Harvey #define REG_BLK_BU 0x00dc 1009ac0038dSTim Harvey #define REG_BLK_RV 0x00de 1019ac0038dSTim Harvey #define REG_FILTERS_CTRL 0x00e0 1029ac0038dSTim Harvey #define REG_DITHERING_CTRL 0x00E9 1039ac0038dSTim Harvey #define REG_OF 0x00EA 1049ac0038dSTim Harvey #define REG_PCLK 0x00EB 1059ac0038dSTim Harvey #define REG_HS_HREF 0x00EC 1069ac0038dSTim Harvey #define REG_VS_VREF 0x00ED 1079ac0038dSTim Harvey #define REG_DE_FREF 0x00EE 1089ac0038dSTim Harvey #define REG_VP35_32_CTRL 0x00EF 1099ac0038dSTim Harvey #define REG_VP31_28_CTRL 0x00F0 1109ac0038dSTim Harvey #define REG_VP27_24_CTRL 0x00F1 1119ac0038dSTim Harvey #define REG_VP23_20_CTRL 0x00F2 1129ac0038dSTim Harvey #define REG_VP19_16_CTRL 0x00F3 1139ac0038dSTim Harvey #define REG_VP15_12_CTRL 0x00F4 1149ac0038dSTim Harvey #define REG_VP11_08_CTRL 0x00F5 1159ac0038dSTim Harvey #define REG_VP07_04_CTRL 0x00F6 1169ac0038dSTim Harvey #define REG_VP03_00_CTRL 0x00F7 1179ac0038dSTim Harvey #define REG_CURPAGE_00H 0xFF 1189ac0038dSTim Harvey 1199ac0038dSTim Harvey #define MASK_VPER 0x3fffff 120*d64a7709SKrzysztof Hałasa #define MASK_VPER_SYNC_POS 0x800000 1219ac0038dSTim Harvey #define MASK_VHREF 0x3fff 1229ac0038dSTim Harvey #define MASK_HPER 0x0fff 123*d64a7709SKrzysztof Hałasa #define MASK_HPER_SYNC_POS 0x8000 1249ac0038dSTim Harvey #define MASK_HSWIDTH 0x03ff 125*d64a7709SKrzysztof Hałasa #define MASK_HSWIDTH_INTERLACED 0x8000 1269ac0038dSTim Harvey 1279ac0038dSTim Harvey /* HPD Detection */ 1289ac0038dSTim Harvey #define DETECT_UTIL BIT(7) /* utility of HDMI level */ 1299ac0038dSTim Harvey #define DETECT_HPD BIT(6) /* HPD of HDMI level */ 1309ac0038dSTim Harvey #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */ 1319ac0038dSTim Harvey #define DETECT_5V_B BIT(1) /* 5V present on input B */ 1329ac0038dSTim Harvey #define DETECT_5V_A BIT(0) /* 5V present on input A */ 1339ac0038dSTim Harvey 1349ac0038dSTim Harvey /* Input Select */ 1359ac0038dSTim Harvey #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */ 1369ac0038dSTim Harvey #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */ 1379ac0038dSTim Harvey #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */ 1389ac0038dSTim Harvey #define INPUT_SEL_B BIT(0) /* 0=inputA 1=inputB */ 1399ac0038dSTim Harvey 1409ac0038dSTim Harvey /* Service Mode */ 1419ac0038dSTim Harvey #define SVC_MODE_CLK2_MASK 0xc0 1429ac0038dSTim Harvey #define SVC_MODE_CLK2_SHIFT 6 1439ac0038dSTim Harvey #define SVC_MODE_CLK2_XTL 0L 1449ac0038dSTim Harvey #define SVC_MODE_CLK2_XTLDIV2 1L 1459ac0038dSTim Harvey #define SVC_MODE_CLK2_HDMIX2 3L 1469ac0038dSTim Harvey #define SVC_MODE_CLK1_MASK 0x30 1479ac0038dSTim Harvey #define SVC_MODE_CLK1_SHIFT 4 1489ac0038dSTim Harvey #define SVC_MODE_CLK1_XTAL 0L 1499ac0038dSTim Harvey #define SVC_MODE_CLK1_XTLDIV2 1L 1509ac0038dSTim Harvey #define SVC_MODE_CLK1_HDMI 3L 1519ac0038dSTim Harvey #define SVC_MODE_RAMP BIT(3) /* 0=colorbar 1=ramp */ 1529ac0038dSTim Harvey #define SVC_MODE_PAL BIT(2) /* 0=NTSC(480i/p) 1=PAL(576i/p) */ 1539ac0038dSTim Harvey #define SVC_MODE_INT_PROG BIT(1) /* 0=interlaced 1=progressive */ 1549ac0038dSTim Harvey #define SVC_MODE_SM_ON BIT(0) /* Enable color bars and tone gen */ 1559ac0038dSTim Harvey 1569ac0038dSTim Harvey /* HDP Manual Control */ 1579ac0038dSTim Harvey #define HPD_MAN_CTRL_HPD_PULSE BIT(7) /* HPD Pulse low 110ms */ 1589ac0038dSTim Harvey #define HPD_MAN_CTRL_5VEN BIT(2) /* Output 5V */ 1599ac0038dSTim Harvey #define HPD_MAN_CTRL_HPD_B BIT(1) /* Assert HPD High for Input A */ 1609ac0038dSTim Harvey #define HPD_MAN_CTRL_HPD_A BIT(0) /* Assert HPD High for Input A */ 1619ac0038dSTim Harvey 1629ac0038dSTim Harvey /* RT_MAN_CTRL */ 1639ac0038dSTim Harvey #define RT_MAN_CTRL_RT_AUTO BIT(7) 1649ac0038dSTim Harvey #define RT_MAN_CTRL_RT BIT(6) 1659ac0038dSTim Harvey #define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */ 1669ac0038dSTim Harvey #define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */ 1679ac0038dSTim Harvey 1689ac0038dSTim Harvey /* VDP_CTRL */ 1699ac0038dSTim Harvey #define VDP_CTRL_COMPDEL_BP BIT(5) /* bypass compdel */ 1709ac0038dSTim Harvey #define VDP_CTRL_FORMATTER_BP BIT(4) /* bypass formatter */ 1719ac0038dSTim Harvey #define VDP_CTRL_PREFILTER_BP BIT(1) /* bypass prefilter */ 1729ac0038dSTim Harvey #define VDP_CTRL_MATRIX_BP BIT(0) /* bypass matrix conversion */ 1739ac0038dSTim Harvey 1749ac0038dSTim Harvey /* REG_VHREF_CTRL */ 1759ac0038dSTim Harvey #define VHREF_INT_DET BIT(7) /* interlace detect: 1=alt 0=frame */ 1769ac0038dSTim Harvey #define VHREF_VSYNC_MASK 0x60 1779ac0038dSTim Harvey #define VHREF_VSYNC_SHIFT 6 1789ac0038dSTim Harvey #define VHREF_VSYNC_AUTO 0L 1799ac0038dSTim Harvey #define VHREF_VSYNC_FDW 1L 1809ac0038dSTim Harvey #define VHREF_VSYNC_EVEN 2L 1819ac0038dSTim Harvey #define VHREF_VSYNC_ODD 3L 1829ac0038dSTim Harvey #define VHREF_STD_DET_MASK 0x18 1839ac0038dSTim Harvey #define VHREF_STD_DET_SHIFT 3 1849ac0038dSTim Harvey #define VHREF_STD_DET_PAL 0L 1859ac0038dSTim Harvey #define VHREF_STD_DET_NTSC 1L 1869ac0038dSTim Harvey #define VHREF_STD_DET_AUTO 2L 1879ac0038dSTim Harvey #define VHREF_STD_DET_OFF 3L 1889ac0038dSTim Harvey #define VHREF_VREF_SRC_STD BIT(2) /* 1=from standard 0=manual */ 1899ac0038dSTim Harvey #define VHREF_HREF_SRC_STD BIT(1) /* 1=from standard 0=manual */ 1909ac0038dSTim Harvey #define VHREF_HSYNC_SEL_HS BIT(0) /* 1=HS 0=VS */ 1919ac0038dSTim Harvey 1929ac0038dSTim Harvey /* AUDIO_OUT_ENABLE */ 1939ac0038dSTim Harvey #define AUDIO_OUT_ENABLE_ACLK BIT(5) 1949ac0038dSTim Harvey #define AUDIO_OUT_ENABLE_WS BIT(4) 1959ac0038dSTim Harvey #define AUDIO_OUT_ENABLE_AP3 BIT(3) 1969ac0038dSTim Harvey #define AUDIO_OUT_ENABLE_AP2 BIT(2) 1979ac0038dSTim Harvey #define AUDIO_OUT_ENABLE_AP1 BIT(1) 1989ac0038dSTim Harvey #define AUDIO_OUT_ENABLE_AP0 BIT(0) 1999ac0038dSTim Harvey 2009ac0038dSTim Harvey /* Prefilter Control */ 2019ac0038dSTim Harvey #define FILTERS_CTRL_BU_MASK 0x0c 2029ac0038dSTim Harvey #define FILTERS_CTRL_BU_SHIFT 2 2039ac0038dSTim Harvey #define FILTERS_CTRL_RV_MASK 0x03 2049ac0038dSTim Harvey #define FILTERS_CTRL_RV_SHIFT 0 2059ac0038dSTim Harvey #define FILTERS_CTRL_OFF 0L /* off */ 2069ac0038dSTim Harvey #define FILTERS_CTRL_2TAP 1L /* 2 Taps */ 2079ac0038dSTim Harvey #define FILTERS_CTRL_7TAP 2L /* 7 Taps */ 2089ac0038dSTim Harvey #define FILTERS_CTRL_2_7TAP 3L /* 2/7 Taps */ 2099ac0038dSTim Harvey 2109ac0038dSTim Harvey /* PCLK Configuration */ 2119ac0038dSTim Harvey #define PCLK_DELAY_MASK 0x70 2129ac0038dSTim Harvey #define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ 2139ac0038dSTim Harvey #define PCLK_INV_SHIFT 2 2149ac0038dSTim Harvey #define PCLK_SEL_MASK 0x03 /* clock scaler */ 2159ac0038dSTim Harvey #define PCLK_SEL_SHIFT 0 2169ac0038dSTim Harvey #define PCLK_SEL_X1 0L 2179ac0038dSTim Harvey #define PCLK_SEL_X2 1L 2189ac0038dSTim Harvey #define PCLK_SEL_DIV2 2L 2199ac0038dSTim Harvey #define PCLK_SEL_DIV4 3L 2209ac0038dSTim Harvey 2219ac0038dSTim Harvey /* Pixel Repeater */ 2229ac0038dSTim Harvey #define PIX_REPEAT_MASK_UP_SEL 0x30 2239ac0038dSTim Harvey #define PIX_REPEAT_MASK_REP 0x0f 2249ac0038dSTim Harvey #define PIX_REPEAT_SHIFT 4 2259ac0038dSTim Harvey #define PIX_REPEAT_CHROMA 1 2269ac0038dSTim Harvey 2279ac0038dSTim Harvey /* Page 0x01 - HDMI info and packets */ 2289ac0038dSTim Harvey #define REG_HDMI_FLAGS 0x0100 2299ac0038dSTim Harvey #define REG_DEEP_COLOR_MODE 0x0101 2309ac0038dSTim Harvey #define REG_AUDIO_FLAGS 0x0108 2319ac0038dSTim Harvey #define REG_AUDIO_FREQ 0x0109 2329ac0038dSTim Harvey #define REG_ACP_PACKET_TYPE 0x0141 2339ac0038dSTim Harvey #define REG_ISRC1_PACKET_TYPE 0x0161 2349ac0038dSTim Harvey #define REG_ISRC2_PACKET_TYPE 0x0181 2359ac0038dSTim Harvey #define REG_GBD_PACKET_TYPE 0x01a1 2369ac0038dSTim Harvey 2379ac0038dSTim Harvey /* HDMI_FLAGS */ 2389ac0038dSTim Harvey #define HDMI_FLAGS_AUDIO BIT(7) /* Audio packet in last videoframe */ 2399ac0038dSTim Harvey #define HDMI_FLAGS_HDMI BIT(6) /* HDMI detected */ 2409ac0038dSTim Harvey #define HDMI_FLAGS_EESS BIT(5) /* EESS detected */ 2419ac0038dSTim Harvey #define HDMI_FLAGS_HDCP BIT(4) /* HDCP detected */ 2429ac0038dSTim Harvey #define HDMI_FLAGS_AVMUTE BIT(3) /* AVMUTE */ 2439ac0038dSTim Harvey #define HDMI_FLAGS_AUD_LAYOUT BIT(2) /* Layout status Audio sample packet */ 2449ac0038dSTim Harvey #define HDMI_FLAGS_AUD_FIFO_OF BIT(1) /* FIFO read/write pointers crossed */ 2459ac0038dSTim Harvey #define HDMI_FLAGS_AUD_FIFO_LOW BIT(0) /* FIFO read ptr within 2 of write */ 2469ac0038dSTim Harvey 2479ac0038dSTim Harvey /* Page 0x12 - HDMI Extra control and debug */ 2489ac0038dSTim Harvey #define REG_CLK_CFG 0x1200 2499ac0038dSTim Harvey #define REG_CLK_OUT_CFG 0x1201 2509ac0038dSTim Harvey #define REG_CFG1 0x1202 2519ac0038dSTim Harvey #define REG_CFG2 0x1203 2529ac0038dSTim Harvey #define REG_WDL_CFG 0x1210 2539ac0038dSTim Harvey #define REG_DELOCK_DELAY 0x1212 2549ac0038dSTim Harvey #define REG_PON_OVR_EN 0x12A0 2559ac0038dSTim Harvey #define REG_PON_CBIAS 0x12A1 2569ac0038dSTim Harvey #define REG_PON_RESCAL 0x12A2 2579ac0038dSTim Harvey #define REG_PON_RES 0x12A3 2589ac0038dSTim Harvey #define REG_PON_CLK 0x12A4 2599ac0038dSTim Harvey #define REG_PON_PLL 0x12A5 2609ac0038dSTim Harvey #define REG_PON_EQ 0x12A6 2619ac0038dSTim Harvey #define REG_PON_DES 0x12A7 2629ac0038dSTim Harvey #define REG_PON_OUT 0x12A8 2639ac0038dSTim Harvey #define REG_PON_MUX 0x12A9 2649ac0038dSTim Harvey #define REG_MODE_REC_CFG1 0x12F8 2659ac0038dSTim Harvey #define REG_MODE_REC_CFG2 0x12F9 2669ac0038dSTim Harvey #define REG_MODE_REC_STS 0x12FA 2679ac0038dSTim Harvey #define REG_AUDIO_LAYOUT 0x12D0 2689ac0038dSTim Harvey 2699ac0038dSTim Harvey #define PON_EN 1 2709ac0038dSTim Harvey #define PON_DIS 0 2719ac0038dSTim Harvey 2729ac0038dSTim Harvey /* CLK CFG */ 2739ac0038dSTim Harvey #define CLK_CFG_INV_OUT_CLK BIT(7) 2749ac0038dSTim Harvey #define CLK_CFG_INV_BUS_CLK BIT(6) 2759ac0038dSTim Harvey #define CLK_CFG_SEL_ACLK_EN BIT(1) 2769ac0038dSTim Harvey #define CLK_CFG_SEL_ACLK BIT(0) 2779ac0038dSTim Harvey #define CLK_CFG_DIS 0 2789ac0038dSTim Harvey 2799ac0038dSTim Harvey /* Page 0x13 - HDMI Extra control and debug */ 2809ac0038dSTim Harvey #define REG_DEEP_COLOR_CTRL 0x1300 2819ac0038dSTim Harvey #define REG_CGU_DBG_SEL 0x1305 2829ac0038dSTim Harvey #define REG_HDCP_DDC_ADDR 0x1310 2839ac0038dSTim Harvey #define REG_HDCP_KIDX 0x1316 2849ac0038dSTim Harvey #define REG_DEEP_PLL7_BYP 0x1347 2859ac0038dSTim Harvey #define REG_HDCP_DE_CTRL 0x1370 2869ac0038dSTim Harvey #define REG_HDCP_EP_FILT_CTRL 0x1371 2879ac0038dSTim Harvey #define REG_HDMI_CTRL 0x1377 2889ac0038dSTim Harvey #define REG_HMTP_CTRL 0x137a 2899ac0038dSTim Harvey #define REG_TIMER_D 0x13CF 2909ac0038dSTim Harvey #define REG_SUS_SET_RGB0 0x13E1 2919ac0038dSTim Harvey #define REG_SUS_SET_RGB1 0x13E2 2929ac0038dSTim Harvey #define REG_SUS_SET_RGB2 0x13E3 2939ac0038dSTim Harvey #define REG_SUS_SET_RGB3 0x13E4 2949ac0038dSTim Harvey #define REG_SUS_SET_RGB4 0x13E5 2959ac0038dSTim Harvey #define REG_MAN_SUS_HDMI_SEL 0x13E8 2969ac0038dSTim Harvey #define REG_MAN_HDMI_SET 0x13E9 2979ac0038dSTim Harvey #define REG_SUS_CLOCK_GOOD 0x13EF 2989ac0038dSTim Harvey 2999ac0038dSTim Harvey /* HDCP DE Control */ 3009ac0038dSTim Harvey #define HDCP_DE_MODE_MASK 0xc0 /* DE Measurement mode */ 3019ac0038dSTim Harvey #define HDCP_DE_MODE_SHIFT 6 3029ac0038dSTim Harvey #define HDCP_DE_REGEN_EN BIT(5) /* enable regen mode */ 3039ac0038dSTim Harvey #define HDCP_DE_FILTER_MASK 0x18 /* DE filter sensitivity */ 3049ac0038dSTim Harvey #define HDCP_DE_FILTER_SHIFT 3 3059ac0038dSTim Harvey #define HDCP_DE_COMP_MASK 0x07 /* DE Composition mode */ 3069ac0038dSTim Harvey #define HDCP_DE_COMP_MIXED 6L 3079ac0038dSTim Harvey #define HDCP_DE_COMP_OR 5L 3089ac0038dSTim Harvey #define HDCP_DE_COMP_AND 4L 3099ac0038dSTim Harvey #define HDCP_DE_COMP_CH3 3L 3109ac0038dSTim Harvey #define HDCP_DE_COMP_CH2 2L 3119ac0038dSTim Harvey #define HDCP_DE_COMP_CH1 1L 3129ac0038dSTim Harvey #define HDCP_DE_COMP_CH0 0L 3139ac0038dSTim Harvey 3149ac0038dSTim Harvey /* HDCP EP Filter Control */ 3159ac0038dSTim Harvey #define HDCP_EP_FIL_CTL_MASK 0x30 3169ac0038dSTim Harvey #define HDCP_EP_FIL_CTL_SHIFT 4 3179ac0038dSTim Harvey #define HDCP_EP_FIL_VS_MASK 0x0c 3189ac0038dSTim Harvey #define HDCP_EP_FIL_VS_SHIFT 2 3199ac0038dSTim Harvey #define HDCP_EP_FIL_HS_MASK 0x03 3209ac0038dSTim Harvey #define HDCP_EP_FIL_HS_SHIFT 0 3219ac0038dSTim Harvey 3229ac0038dSTim Harvey /* HDMI_CTRL */ 3239ac0038dSTim Harvey #define HDMI_CTRL_MUTE_MASK 0x0c 3249ac0038dSTim Harvey #define HDMI_CTRL_MUTE_SHIFT 2 3259ac0038dSTim Harvey #define HDMI_CTRL_MUTE_AUTO 0L 3269ac0038dSTim Harvey #define HDMI_CTRL_MUTE_OFF 1L 3279ac0038dSTim Harvey #define HDMI_CTRL_MUTE_ON 2L 3289ac0038dSTim Harvey #define HDMI_CTRL_HDCP_MASK 0x03 3299ac0038dSTim Harvey #define HDMI_CTRL_HDCP_SHIFT 0 3309ac0038dSTim Harvey #define HDMI_CTRL_HDCP_EESS 2L 3319ac0038dSTim Harvey #define HDMI_CTRL_HDCP_OESS 1L 3329ac0038dSTim Harvey #define HDMI_CTRL_HDCP_AUTO 0L 3339ac0038dSTim Harvey 3349ac0038dSTim Harvey /* CGU_DBG_SEL bits */ 3359ac0038dSTim Harvey #define CGU_DBG_CLK_SEL_MASK 0x18 3369ac0038dSTim Harvey #define CGU_DBG_CLK_SEL_SHIFT 3 3379ac0038dSTim Harvey #define CGU_DBG_XO_FRO_SEL BIT(2) 3389ac0038dSTim Harvey #define CGU_DBG_VDP_CLK_SEL BIT(1) 3399ac0038dSTim Harvey #define CGU_DBG_PIX_CLK_SEL BIT(0) 3409ac0038dSTim Harvey 3419ac0038dSTim Harvey /* REG_MAN_SUS_HDMI_SEL / REG_MAN_HDMI_SET bits */ 3429ac0038dSTim Harvey #define MAN_DIS_OUT_BUF BIT(7) 3439ac0038dSTim Harvey #define MAN_DIS_ANA_PATH BIT(6) 3449ac0038dSTim Harvey #define MAN_DIS_HDCP BIT(5) 3459ac0038dSTim Harvey #define MAN_DIS_TMDS_ENC BIT(4) 3469ac0038dSTim Harvey #define MAN_DIS_TMDS_FLOW BIT(3) 3479ac0038dSTim Harvey #define MAN_RST_HDCP BIT(2) 3489ac0038dSTim Harvey #define MAN_RST_TMDS_ENC BIT(1) 3499ac0038dSTim Harvey #define MAN_RST_TMDS_FLOW BIT(0) 3509ac0038dSTim Harvey 3519ac0038dSTim Harvey /* Page 0x14 - Audio Extra control and debug */ 3529ac0038dSTim Harvey #define REG_FIFO_LATENCY_VAL 0x1403 3539ac0038dSTim Harvey #define REG_AUDIO_CLOCK 0x1411 3549ac0038dSTim Harvey #define REG_TEST_NCTS_CTRL 0x1415 3559ac0038dSTim Harvey #define REG_TEST_AUDIO_FREQ 0x1426 3569ac0038dSTim Harvey #define REG_TEST_MODE 0x1437 3579ac0038dSTim Harvey 3589ac0038dSTim Harvey /* Audio Clock Configuration */ 3599ac0038dSTim Harvey #define AUDIO_CLOCK_PLL_PD BIT(7) /* powerdown PLL */ 3609ac0038dSTim Harvey #define AUDIO_CLOCK_SEL_MASK 0x7f 3619ac0038dSTim Harvey #define AUDIO_CLOCK_SEL_16FS 0L /* 16*fs */ 3629ac0038dSTim Harvey #define AUDIO_CLOCK_SEL_32FS 1L /* 32*fs */ 3639ac0038dSTim Harvey #define AUDIO_CLOCK_SEL_64FS 2L /* 64*fs */ 3649ac0038dSTim Harvey #define AUDIO_CLOCK_SEL_128FS 3L /* 128*fs */ 3659ac0038dSTim Harvey #define AUDIO_CLOCK_SEL_256FS 4L /* 256*fs */ 3669ac0038dSTim Harvey #define AUDIO_CLOCK_SEL_512FS 5L /* 512*fs */ 3679ac0038dSTim Harvey 3689ac0038dSTim Harvey /* Page 0x20: EDID and Hotplug Detect */ 3699ac0038dSTim Harvey #define REG_EDID_IN_BYTE0 0x2000 /* EDID base */ 3709ac0038dSTim Harvey #define REG_EDID_IN_VERSION 0x2080 3719ac0038dSTim Harvey #define REG_EDID_ENABLE 0x2081 3729ac0038dSTim Harvey #define REG_HPD_POWER 0x2084 3739ac0038dSTim Harvey #define REG_HPD_AUTO_CTRL 0x2085 3749ac0038dSTim Harvey #define REG_HPD_DURATION 0x2086 3759ac0038dSTim Harvey #define REG_RX_HPD_HEAC 0x2087 3769ac0038dSTim Harvey 3779ac0038dSTim Harvey /* EDID_ENABLE */ 3789ac0038dSTim Harvey #define EDID_ENABLE_NACK_OFF BIT(7) 3799ac0038dSTim Harvey #define EDID_ENABLE_EDID_ONLY BIT(6) 3809ac0038dSTim Harvey #define EDID_ENABLE_B_EN BIT(1) 3819ac0038dSTim Harvey #define EDID_ENABLE_A_EN BIT(0) 3829ac0038dSTim Harvey 3839ac0038dSTim Harvey /* HPD Power */ 3849ac0038dSTim Harvey #define HPD_POWER_BP_MASK 0x0c 3859ac0038dSTim Harvey #define HPD_POWER_BP_SHIFT 2 3869ac0038dSTim Harvey #define HPD_POWER_BP_LOW 0L 3879ac0038dSTim Harvey #define HPD_POWER_BP_HIGH 1L 3889ac0038dSTim Harvey #define HPD_POWER_EDID_ONLY BIT(1) 3899ac0038dSTim Harvey 3909ac0038dSTim Harvey /* HPD Auto control */ 3919ac0038dSTim Harvey #define HPD_AUTO_READ_EDID BIT(7) 3929ac0038dSTim Harvey #define HPD_AUTO_HPD_F3TECH BIT(5) 3939ac0038dSTim Harvey #define HPD_AUTO_HP_OTHER BIT(4) 3949ac0038dSTim Harvey #define HPD_AUTO_HPD_UNSEL BIT(3) 3959ac0038dSTim Harvey #define HPD_AUTO_HPD_ALL_CH BIT(2) 3969ac0038dSTim Harvey #define HPD_AUTO_HPD_PRV_CH BIT(1) 3979ac0038dSTim Harvey #define HPD_AUTO_HPD_NEW_CH BIT(0) 3989ac0038dSTim Harvey 3999ac0038dSTim Harvey /* Page 0x21 - EDID content */ 4009ac0038dSTim Harvey #define REG_EDID_IN_BYTE128 0x2100 /* CEA Extension block */ 4019ac0038dSTim Harvey #define REG_EDID_IN_SPA_SUB 0x2180 4029ac0038dSTim Harvey #define REG_EDID_IN_SPA_AB_A 0x2181 4039ac0038dSTim Harvey #define REG_EDID_IN_SPA_CD_A 0x2182 4049ac0038dSTim Harvey #define REG_EDID_IN_CKSUM_A 0x2183 4059ac0038dSTim Harvey #define REG_EDID_IN_SPA_AB_B 0x2184 4069ac0038dSTim Harvey #define REG_EDID_IN_SPA_CD_B 0x2185 4079ac0038dSTim Harvey #define REG_EDID_IN_CKSUM_B 0x2186 4089ac0038dSTim Harvey 4099ac0038dSTim Harvey /* Page 0x30 - NV Configuration */ 4109ac0038dSTim Harvey #define REG_RT_AUTO_CTRL 0x3000 4119ac0038dSTim Harvey #define REG_EQ_MAN_CTRL0 0x3001 4129ac0038dSTim Harvey #define REG_EQ_MAN_CTRL1 0x3002 4139ac0038dSTim Harvey #define REG_OUTPUT_CFG 0x3003 4149ac0038dSTim Harvey #define REG_MUTE_CTRL 0x3004 4159ac0038dSTim Harvey #define REG_SLAVE_ADDR 0x3005 4169ac0038dSTim Harvey #define REG_CMTP_REG6 0x3006 4179ac0038dSTim Harvey #define REG_CMTP_REG7 0x3007 4189ac0038dSTim Harvey #define REG_CMTP_REG8 0x3008 4199ac0038dSTim Harvey #define REG_CMTP_REG9 0x3009 4209ac0038dSTim Harvey #define REG_CMTP_REGA 0x300A 4219ac0038dSTim Harvey #define REG_CMTP_REGB 0x300B 4229ac0038dSTim Harvey #define REG_CMTP_REGC 0x300C 4239ac0038dSTim Harvey #define REG_CMTP_REGD 0x300D 4249ac0038dSTim Harvey #define REG_CMTP_REGE 0x300E 4259ac0038dSTim Harvey #define REG_CMTP_REGF 0x300F 4269ac0038dSTim Harvey #define REG_CMTP_REG10 0x3010 4279ac0038dSTim Harvey #define REG_CMTP_REG11 0x3011 4289ac0038dSTim Harvey 4299ac0038dSTim Harvey /* Page 0x80 - CEC */ 4309ac0038dSTim Harvey #define REG_PWR_CONTROL 0x80F4 4319ac0038dSTim Harvey #define REG_OSC_DIVIDER 0x80F5 4329ac0038dSTim Harvey #define REG_EN_OSC_PERIOD_LSB 0x80F8 4339ac0038dSTim Harvey #define REG_CONTROL 0x80FF 4349ac0038dSTim Harvey 4359ac0038dSTim Harvey /* global interrupt flags (INT_FLG_CRL_TOP) */ 4369ac0038dSTim Harvey #define INTERRUPT_AFE BIT(7) /* AFE module */ 4379ac0038dSTim Harvey #define INTERRUPT_HDCP BIT(6) /* HDCP module */ 4389ac0038dSTim Harvey #define INTERRUPT_AUDIO BIT(5) /* Audio module */ 4399ac0038dSTim Harvey #define INTERRUPT_INFO BIT(4) /* Infoframe module */ 4409ac0038dSTim Harvey #define INTERRUPT_MODE BIT(3) /* HDMI mode module */ 4419ac0038dSTim Harvey #define INTERRUPT_RATE BIT(2) /* rate module */ 4429ac0038dSTim Harvey #define INTERRUPT_DDC BIT(1) /* DDC module */ 4439ac0038dSTim Harvey #define INTERRUPT_SUS BIT(0) /* SUS module */ 4449ac0038dSTim Harvey 4459ac0038dSTim Harvey /* INT_FLG_CLR_HDCP bits */ 4469ac0038dSTim Harvey #define MASK_HDCP_MTP BIT(7) /* HDCP MTP busy */ 4479ac0038dSTim Harvey #define MASK_HDCP_DLMTP BIT(4) /* HDCP end download MTP to SRAM */ 4489ac0038dSTim Harvey #define MASK_HDCP_DLRAM BIT(3) /* HDCP end download keys from SRAM */ 4499ac0038dSTim Harvey #define MASK_HDCP_ENC BIT(2) /* HDCP ENC */ 4509ac0038dSTim Harvey #define MASK_STATE_C5 BIT(1) /* HDCP State C5 reached */ 4519ac0038dSTim Harvey #define MASK_AKSV BIT(0) /* AKSV received (start of auth) */ 4529ac0038dSTim Harvey 4539ac0038dSTim Harvey /* INT_FLG_CLR_RATE bits */ 4549ac0038dSTim Harvey #define MASK_RATE_B_DRIFT BIT(7) /* Rate measurement drifted */ 4559ac0038dSTim Harvey #define MASK_RATE_B_ST BIT(6) /* Rate measurement stability change */ 4569ac0038dSTim Harvey #define MASK_RATE_B_ACT BIT(5) /* Rate measurement activity change */ 4579ac0038dSTim Harvey #define MASK_RATE_B_PST BIT(4) /* Rate measreument presence change */ 4589ac0038dSTim Harvey #define MASK_RATE_A_DRIFT BIT(3) /* Rate measurement drifted */ 4599ac0038dSTim Harvey #define MASK_RATE_A_ST BIT(2) /* Rate measurement stability change */ 4609ac0038dSTim Harvey #define MASK_RATE_A_ACT BIT(1) /* Rate measurement presence change */ 4619ac0038dSTim Harvey #define MASK_RATE_A_PST BIT(0) /* Rate measreument presence change */ 4629ac0038dSTim Harvey 4639ac0038dSTim Harvey /* INT_FLG_CLR_SUS (Start Up Sequencer) bits */ 4649ac0038dSTim Harvey #define MASK_MPT BIT(7) /* Config MTP end of process */ 4659ac0038dSTim Harvey #define MASK_FMT BIT(5) /* Video format changed */ 4669ac0038dSTim Harvey #define MASK_RT_PULSE BIT(4) /* End of termination resistance pulse */ 4679ac0038dSTim Harvey #define MASK_SUS_END BIT(3) /* SUS last state reached */ 4689ac0038dSTim Harvey #define MASK_SUS_ACT BIT(2) /* Activity of selected input changed */ 4699ac0038dSTim Harvey #define MASK_SUS_CH BIT(1) /* Selected input changed */ 4709ac0038dSTim Harvey #define MASK_SUS_ST BIT(0) /* SUS state changed */ 4719ac0038dSTim Harvey 4729ac0038dSTim Harvey /* INT_FLG_CLR_DDC bits */ 4739ac0038dSTim Harvey #define MASK_EDID_MTP BIT(7) /* EDID MTP end of process */ 4749ac0038dSTim Harvey #define MASK_DDC_ERR BIT(6) /* master DDC error */ 4759ac0038dSTim Harvey #define MASK_DDC_CMD_DONE BIT(5) /* master DDC cmd send correct */ 4769ac0038dSTim Harvey #define MASK_READ_DONE BIT(4) /* End of down EDID read */ 4779ac0038dSTim Harvey #define MASK_RX_DDC_SW BIT(3) /* Output DDC switching finished */ 4789ac0038dSTim Harvey #define MASK_HDCP_DDC_SW BIT(2) /* HDCP DDC switching finished */ 4799ac0038dSTim Harvey #define MASK_HDP_PULSE_END BIT(1) /* End of Hot Plug Detect pulse */ 4809ac0038dSTim Harvey #define MASK_DET_5V BIT(0) /* Detection of +5V */ 4819ac0038dSTim Harvey 4829ac0038dSTim Harvey /* INT_FLG_CLR_MODE bits */ 4839ac0038dSTim Harvey #define MASK_HDMI_FLG BIT(7) /* HDMI mode/avmute/encrypt/FIFO fail */ 4849ac0038dSTim Harvey #define MASK_GAMUT BIT(6) /* Gamut packet */ 4859ac0038dSTim Harvey #define MASK_ISRC2 BIT(5) /* ISRC2 packet */ 4869ac0038dSTim Harvey #define MASK_ISRC1 BIT(4) /* ISRC1 packet */ 4879ac0038dSTim Harvey #define MASK_ACP BIT(3) /* Audio Content Protection packet */ 4889ac0038dSTim Harvey #define MASK_DC_NO_GCP BIT(2) /* GCP not received in 5 frames */ 4899ac0038dSTim Harvey #define MASK_DC_PHASE BIT(1) /* deepcolor pixel phase needs update */ 4909ac0038dSTim Harvey #define MASK_DC_MODE BIT(0) /* deepcolor color depth changed */ 4919ac0038dSTim Harvey 4929ac0038dSTim Harvey /* INT_FLG_CLR_INFO bits (Infoframe Change Status) */ 4939ac0038dSTim Harvey #define MASK_MPS_IF BIT(6) /* MPEG Source Product */ 4949ac0038dSTim Harvey #define MASK_AUD_IF BIT(5) /* Audio */ 4959ac0038dSTim Harvey #define MASK_SPD_IF BIT(4) /* Source Product Descriptor */ 4969ac0038dSTim Harvey #define MASK_AVI_IF BIT(3) /* Auxiliary Video IF */ 4979ac0038dSTim Harvey #define MASK_VS_IF_OTHER_BK2 BIT(2) /* Vendor Specific (bank2) */ 4989ac0038dSTim Harvey #define MASK_VS_IF_OTHER_BK1 BIT(1) /* Vendor Specific (bank1) */ 4999ac0038dSTim Harvey #define MASK_VS_IF_HDMI BIT(0) /* Vendor Specific (w/ HDMI LLC code) */ 5009ac0038dSTim Harvey 5019ac0038dSTim Harvey /* INT_FLG_CLR_AUDIO bits */ 5029ac0038dSTim Harvey #define MASK_AUDIO_FREQ_FLG BIT(5) /* Audio freq change */ 5039ac0038dSTim Harvey #define MASK_AUDIO_FLG BIT(4) /* DST, OBA, HBR, ASP change */ 5049ac0038dSTim Harvey #define MASK_MUTE_FLG BIT(3) /* Audio Mute */ 5059ac0038dSTim Harvey #define MASK_CH_STATE BIT(2) /* Channel status */ 5069ac0038dSTim Harvey #define MASK_UNMUTE_FIFO BIT(1) /* Audio Unmute */ 5079ac0038dSTim Harvey #define MASK_ERROR_FIFO_PT BIT(0) /* Audio FIFO pointer error */ 5089ac0038dSTim Harvey 5099ac0038dSTim Harvey /* INT_FLG_CLR_AFE bits */ 5109ac0038dSTim Harvey #define MASK_AFE_WDL_UNLOCKED BIT(7) /* Wordlocker was unlocked */ 5119ac0038dSTim Harvey #define MASK_AFE_GAIN_DONE BIT(6) /* Gain calibration done */ 5129ac0038dSTim Harvey #define MASK_AFE_OFFSET_DONE BIT(5) /* Offset calibration done */ 5139ac0038dSTim Harvey #define MASK_AFE_ACTIVITY_DET BIT(4) /* Activity detected on data */ 5149ac0038dSTim Harvey #define MASK_AFE_PLL_LOCK BIT(3) /* TMDS PLL is locked */ 5159ac0038dSTim Harvey #define MASK_AFE_TRMCAL_DONE BIT(2) /* Termination calibration done */ 5169ac0038dSTim Harvey #define MASK_AFE_ASU_STATE BIT(1) /* ASU state is reached */ 5179ac0038dSTim Harvey #define MASK_AFE_ASU_READY BIT(0) /* AFE calibration done: TMDS ready */ 5189ac0038dSTim Harvey 5199ac0038dSTim Harvey /* Audio Output */ 5209ac0038dSTim Harvey #define AUDCFG_CLK_INVERT BIT(7) /* invert A_CLK polarity */ 5219ac0038dSTim Harvey #define AUDCFG_TEST_TONE BIT(6) /* enable test tone generator */ 5229ac0038dSTim Harvey #define AUDCFG_BUS_SHIFT 5 5239ac0038dSTim Harvey #define AUDCFG_BUS_I2S 0L 5249ac0038dSTim Harvey #define AUDCFG_BUS_SPDIF 1L 5259ac0038dSTim Harvey #define AUDCFG_I2SW_SHIFT 4 5269ac0038dSTim Harvey #define AUDCFG_I2SW_16 0L 5279ac0038dSTim Harvey #define AUDCFG_I2SW_32 1L 5289ac0038dSTim Harvey #define AUDCFG_AUTO_MUTE_EN BIT(3) /* Enable Automatic audio mute */ 5299ac0038dSTim Harvey #define AUDCFG_HBR_SHIFT 2 5309ac0038dSTim Harvey #define AUDCFG_HBR_STRAIGHT 0L /* straight via AP0 */ 5319ac0038dSTim Harvey #define AUDCFG_HBR_DEMUX 1L /* demuxed via AP0:AP3 */ 5329ac0038dSTim Harvey #define AUDCFG_TYPE_MASK 0x03 5339ac0038dSTim Harvey #define AUDCFG_TYPE_SHIFT 0 5349ac0038dSTim Harvey #define AUDCFG_TYPE_DST 3L /* Direct Stream Transfer (DST) */ 5359ac0038dSTim Harvey #define AUDCFG_TYPE_OBA 2L /* One Bit Audio (OBA) */ 5369ac0038dSTim Harvey #define AUDCFG_TYPE_HBR 1L /* High Bit Rate (HBR) */ 5379ac0038dSTim Harvey #define AUDCFG_TYPE_PCM 0L /* Audio samples */ 5389ac0038dSTim Harvey 5399ac0038dSTim Harvey /* Video Formatter */ 5409ac0038dSTim Harvey #define OF_VP_ENABLE BIT(7) /* VP[35:0]/HS/VS/DE/CLK */ 5419ac0038dSTim Harvey #define OF_BLK BIT(4) /* blanking codes */ 5429ac0038dSTim Harvey #define OF_TRC BIT(3) /* timing codes (SAV/EAV) */ 5439ac0038dSTim Harvey #define OF_FMT_MASK 0x3 5449ac0038dSTim Harvey #define OF_FMT_444 0L /* RGB444/YUV444 */ 5459ac0038dSTim Harvey #define OF_FMT_422_SMPT 1L /* YUV422 semi-planar */ 5469ac0038dSTim Harvey #define OF_FMT_422_CCIR 2L /* YUV422 CCIR656 */ 5479ac0038dSTim Harvey 5489ac0038dSTim Harvey /* HS/HREF output control */ 5499ac0038dSTim Harvey #define HS_HREF_DELAY_MASK 0xf0 5509ac0038dSTim Harvey #define HS_HREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ 5519ac0038dSTim Harvey #define HS_HREF_PXQ_SHIFT 3 /* Timing codes from HREF */ 5529ac0038dSTim Harvey #define HS_HREF_INV_SHIFT 2 /* polarity (1=invert) */ 5539ac0038dSTim Harvey #define HS_HREF_SEL_MASK 0x03 5549ac0038dSTim Harvey #define HS_HREF_SEL_SHIFT 0 5559ac0038dSTim Harvey #define HS_HREF_SEL_HS_VHREF 0L /* HS from VHREF */ 5569ac0038dSTim Harvey #define HS_HREF_SEL_HREF_VHREF 1L /* HREF from VHREF */ 5579ac0038dSTim Harvey #define HS_HREF_SEL_HREF_HDMI 2L /* HREF from HDMI */ 5589ac0038dSTim Harvey #define HS_HREF_SEL_NONE 3L /* not generated */ 5599ac0038dSTim Harvey 5609ac0038dSTim Harvey /* VS output control */ 5619ac0038dSTim Harvey #define VS_VREF_DELAY_MASK 0xf0 5629ac0038dSTim Harvey #define VS_VREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ 5639ac0038dSTim Harvey #define VS_VREF_INV_SHIFT 2 /* polarity (1=invert) */ 5649ac0038dSTim Harvey #define VS_VREF_SEL_MASK 0x03 5659ac0038dSTim Harvey #define VS_VREF_SEL_SHIFT 0 5669ac0038dSTim Harvey #define VS_VREF_SEL_VS_VHREF 0L /* VS from VHREF */ 5679ac0038dSTim Harvey #define VS_VREF_SEL_VREF_VHREF 1L /* VREF from VHREF */ 5689ac0038dSTim Harvey #define VS_VREF_SEL_VREF_HDMI 2L /* VREF from HDMI */ 5699ac0038dSTim Harvey #define VS_VREF_SEL_NONE 3L /* not generated */ 5709ac0038dSTim Harvey 5719ac0038dSTim Harvey /* DE/FREF output control */ 5729ac0038dSTim Harvey #define DE_FREF_DELAY_MASK 0xf0 5739ac0038dSTim Harvey #define DE_FREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ 5749ac0038dSTim Harvey #define DE_FREF_DE_PXQ_SHIFT 3 /* Timing codes from DE */ 5759ac0038dSTim Harvey #define DE_FREF_INV_SHIFT 2 /* polarity (1=invert) */ 5769ac0038dSTim Harvey #define DE_FREF_SEL_MASK 0x03 5779ac0038dSTim Harvey #define DE_FREF_SEL_SHIFT 0 5789ac0038dSTim Harvey #define DE_FREF_SEL_DE_VHREF 0L /* DE from VHREF (HREF and not(VREF) */ 5799ac0038dSTim Harvey #define DE_FREF_SEL_FREF_VHREF 1L /* FREF from VHREF */ 5809ac0038dSTim Harvey #define DE_FREF_SEL_FREF_HDMI 2L /* FREF from HDMI */ 5819ac0038dSTim Harvey #define DE_FREF_SEL_NONE 3L /* not generated */ 5829ac0038dSTim Harvey 5839ac0038dSTim Harvey /* HDMI_SOFT_RST bits */ 5849ac0038dSTim Harvey #define RESET_DC BIT(7) /* Reset deep color module */ 5859ac0038dSTim Harvey #define RESET_HDCP BIT(6) /* Reset HDCP module */ 5869ac0038dSTim Harvey #define RESET_KSV BIT(5) /* Reset KSV-FIFO */ 5879ac0038dSTim Harvey #define RESET_SCFG BIT(4) /* Reset HDCP and repeater function */ 5889ac0038dSTim Harvey #define RESET_HCFG BIT(3) /* Reset HDCP DDC part */ 5899ac0038dSTim Harvey #define RESET_PA BIT(2) /* Reset polarity adjust */ 5909ac0038dSTim Harvey #define RESET_EP BIT(1) /* Reset Error protection */ 5919ac0038dSTim Harvey #define RESET_TMDS BIT(0) /* Reset TMDS (calib, encoding, flow) */ 5929ac0038dSTim Harvey 5939ac0038dSTim Harvey /* HDMI_INFO_RST bits */ 5949ac0038dSTim Harvey #define NACK_HDCP BIT(7) /* No ACK on HDCP request */ 5959ac0038dSTim Harvey #define RESET_FIFO BIT(4) /* Reset Audio FIFO control */ 5969ac0038dSTim Harvey #define RESET_GAMUT BIT(3) /* Clear Gamut packet */ 5979ac0038dSTim Harvey #define RESET_AI BIT(2) /* Clear ACP and ISRC packets */ 5989ac0038dSTim Harvey #define RESET_IF BIT(1) /* Clear all Audio infoframe packets */ 5999ac0038dSTim Harvey #define RESET_AUDIO BIT(0) /* Reset Audio FIFO control */ 6009ac0038dSTim Harvey 6019ac0038dSTim Harvey /* HDCP_BCAPS bits */ 602f8a7647dSMauro Carvalho Chehab #define HDCP_HDMI BIT(7) /* HDCP supports HDMI (vs DVI only) */ 6039ac0038dSTim Harvey #define HDCP_REPEATER BIT(6) /* HDCP supports repeater function */ 6049ac0038dSTim Harvey #define HDCP_READY BIT(5) /* set by repeater function */ 6059ac0038dSTim Harvey #define HDCP_FAST BIT(4) /* Up to 400kHz */ 6069ac0038dSTim Harvey #define HDCP_11 BIT(1) /* HDCP 1.1 supported */ 6079ac0038dSTim Harvey #define HDCP_FAST_REAUTH BIT(0) /* fast reauthentication supported */ 6089ac0038dSTim Harvey 6099ac0038dSTim Harvey /* Audio output formatter */ 6109ac0038dSTim Harvey #define AUDIO_LAYOUT_SP_FLAG BIT(2) /* sp flag used by FIFO */ 6119ac0038dSTim Harvey #define AUDIO_LAYOUT_MANUAL BIT(1) /* manual layout (vs per pkt) */ 6129ac0038dSTim Harvey #define AUDIO_LAYOUT_LAYOUT1 BIT(0) /* Layout1: AP0-3 vs Layout0:AP0 */ 6139ac0038dSTim Harvey 6149ac0038dSTim Harvey /* masks for interrupt status registers */ 6159ac0038dSTim Harvey #define MASK_SUS_STATUS 0x1F 6169ac0038dSTim Harvey #define LAST_STATE_REACHED 0x1B 6179ac0038dSTim Harvey #define MASK_CLK_STABLE 0x04 6189ac0038dSTim Harvey #define MASK_CLK_ACTIVE 0x02 6199ac0038dSTim Harvey #define MASK_SUS_STATE 0x10 6209ac0038dSTim Harvey #define MASK_SR_FIFO_FIFO_CTRL 0x30 6219ac0038dSTim Harvey #define MASK_AUDIO_FLAG 0x10 6229ac0038dSTim Harvey 6239ac0038dSTim Harvey /* Rate measurement */ 6249ac0038dSTim Harvey #define RATE_REFTIM_ENABLE 0x01 6259ac0038dSTim Harvey #define CLK_MIN_RATE 0x0057e4 6269ac0038dSTim Harvey #define CLK_MAX_RATE 0x0395f8 6279ac0038dSTim Harvey #define WDL_CFG_VAL 0x82 6289ac0038dSTim Harvey #define DC_FILTER_VAL 0x31 6299ac0038dSTim Harvey 6309ac0038dSTim Harvey /* Infoframe */ 6319ac0038dSTim Harvey #define VS_HDMI_IF_UPDATE 0x0200 6329ac0038dSTim Harvey #define VS_HDMI_IF 0x0201 6339ac0038dSTim Harvey #define VS_BK1_IF_UPDATE 0x0220 6349ac0038dSTim Harvey #define VS_BK1_IF 0x0221 6359ac0038dSTim Harvey #define VS_BK2_IF_UPDATE 0x0240 6369ac0038dSTim Harvey #define VS_BK2_IF 0x0241 6379ac0038dSTim Harvey #define AVI_IF_UPDATE 0x0260 6389ac0038dSTim Harvey #define AVI_IF 0x0261 6399ac0038dSTim Harvey #define SPD_IF_UPDATE 0x0280 6409ac0038dSTim Harvey #define SPD_IF 0x0281 6419ac0038dSTim Harvey #define AUD_IF_UPDATE 0x02a0 6429ac0038dSTim Harvey #define AUD_IF 0x02a1 6439ac0038dSTim Harvey #define MPS_IF_UPDATE 0x02c0 6449ac0038dSTim Harvey #define MPS_IF 0x02c1 645