11ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 23f68be7dSNeil Armstrong /* 33f68be7dSNeil Armstrong * Copyright (C) 2016 BayLibre, SAS 43f68be7dSNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com> 53f68be7dSNeil Armstrong * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 63f68be7dSNeil Armstrong */ 73f68be7dSNeil Armstrong 83f68be7dSNeil Armstrong #ifndef __MESON_DW_HDMI_H 93f68be7dSNeil Armstrong #define __MESON_DW_HDMI_H 103f68be7dSNeil Armstrong 113f68be7dSNeil Armstrong /* 123b7c1237SNeil Armstrong * Bit 15-10: RW Reserved. Default 1 starting from G12A 133b7c1237SNeil Armstrong * Bit 9 RW sw_reset_i2c starting from G12A 143b7c1237SNeil Armstrong * Bit 8 RW sw_reset_axiarb starting from G12A 153b7c1237SNeil Armstrong * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A 163b7c1237SNeil Armstrong * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A 173b7c1237SNeil Armstrong * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A 183f68be7dSNeil Armstrong * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset. 193f68be7dSNeil Armstrong * Default 1. 203f68be7dSNeil Armstrong * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset; 213f68be7dSNeil Armstrong * 0=Release from reset. 223f68be7dSNeil Armstrong * Default 1. 233f68be7dSNeil Armstrong * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset. 243f68be7dSNeil Armstrong * Default 1. 253f68be7dSNeil Armstrong * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset; 263f68be7dSNeil Armstrong * 0=Release from reset. Default 1. 273f68be7dSNeil Armstrong * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset; 283f68be7dSNeil Armstrong * 0=Release from reset. Default 1. 293f68be7dSNeil Armstrong */ 303f68be7dSNeil Armstrong #define HDMITX_TOP_SW_RESET (0x000) 313f68be7dSNeil Armstrong 323f68be7dSNeil Armstrong /* 333b7c1237SNeil Armstrong * Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable 343f68be7dSNeil Armstrong * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. 353f68be7dSNeil Armstrong * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. 363f68be7dSNeil Armstrong * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. 373f68be7dSNeil Armstrong * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. 383f68be7dSNeil Armstrong * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. 393b7c1237SNeil Armstrong * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable 403b7c1237SNeil Armstrong * Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable 413b7c1237SNeil Armstrong * Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable 423b7c1237SNeil Armstrong * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A 433f68be7dSNeil Armstrong * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. 443f68be7dSNeil Armstrong * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. 453f68be7dSNeil Armstrong * Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. 463f68be7dSNeil Armstrong * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. 473f68be7dSNeil Armstrong */ 483f68be7dSNeil Armstrong #define HDMITX_TOP_CLK_CNTL (0x001) 493f68be7dSNeil Armstrong 503f68be7dSNeil Armstrong /* 513b7c1237SNeil Armstrong * Bit 31:28 RW rxsense_glitch_width: starting from G12A 523b7c1237SNeil Armstrong * Bit 27:16 RW rxsense_valid_width: starting from G12A 533f68be7dSNeil Armstrong * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. 543f68be7dSNeil Armstrong * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. 553f68be7dSNeil Armstrong */ 563f68be7dSNeil Armstrong #define HDMITX_TOP_HPD_FILTER (0x002) 573f68be7dSNeil Armstrong 583f68be7dSNeil Armstrong /* 593f68be7dSNeil Armstrong * intr_maskn: MASK_N, one bit per interrupt source. 603f68be7dSNeil Armstrong * 1=Enable interrupt source; 0=Disable interrupt source. Default 0. 613b7c1237SNeil Armstrong * [ 7] rxsense_fall starting from G12A 623b7c1237SNeil Armstrong * [ 6] rxsense_rise starting from G12A 633b7c1237SNeil Armstrong * [ 5] err_i2c_timeout starting from G12A 643f68be7dSNeil Armstrong * [ 4] hdcp22_rndnum_err 653f68be7dSNeil Armstrong * [ 3] nonce_rfrsh_rise 663f68be7dSNeil Armstrong * [ 2] hpd_fall_intr 673f68be7dSNeil Armstrong * [ 1] hpd_rise_intr 683f68be7dSNeil Armstrong * [ 0] core_intr 693f68be7dSNeil Armstrong */ 703f68be7dSNeil Armstrong #define HDMITX_TOP_INTR_MASKN (0x003) 713f68be7dSNeil Armstrong 723f68be7dSNeil Armstrong /* 733f68be7dSNeil Armstrong * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt 743f68be7dSNeil Armstrong * bit, read back the interrupt status. 753f68be7dSNeil Armstrong * Bit 31 R IP interrupt status 763b7c1237SNeil Armstrong * Bit 7 RW rxsense_fall starting from G12A 773b7c1237SNeil Armstrong * Bit 6 RW rxsense_rise starting from G12A 783b7c1237SNeil Armstrong * Bit 5 RW err_i2c_timeout starting from G12A 793f68be7dSNeil Armstrong * Bit 2 RW hpd_fall 803f68be7dSNeil Armstrong * Bit 1 RW hpd_rise 813f68be7dSNeil Armstrong * Bit 0 RW IP interrupt 823f68be7dSNeil Armstrong */ 833f68be7dSNeil Armstrong #define HDMITX_TOP_INTR_STAT (0x004) 843f68be7dSNeil Armstrong 853f68be7dSNeil Armstrong /* 863b7c1237SNeil Armstrong * [7] rxsense_fall starting from G12A 873b7c1237SNeil Armstrong * [6] rxsense_rise starting from G12A 883b7c1237SNeil Armstrong * [5] err_i2c_timeout starting from G12A 893f68be7dSNeil Armstrong * [4] hdcp22_rndnum_err 903f68be7dSNeil Armstrong * [3] nonce_rfrsh_rise 913f68be7dSNeil Armstrong * [2] hpd_fall 923f68be7dSNeil Armstrong * [1] hpd_rise 933f68be7dSNeil Armstrong * [0] core_intr_rise 943f68be7dSNeil Armstrong */ 953f68be7dSNeil Armstrong #define HDMITX_TOP_INTR_STAT_CLR (0x005) 963f68be7dSNeil Armstrong 973f68be7dSNeil Armstrong #define HDMITX_TOP_INTR_CORE BIT(0) 983f68be7dSNeil Armstrong #define HDMITX_TOP_INTR_HPD_RISE BIT(1) 993f68be7dSNeil Armstrong #define HDMITX_TOP_INTR_HPD_FALL BIT(2) 1003b7c1237SNeil Armstrong #define HDMITX_TOP_INTR_RXSENSE_RISE BIT(6) 1013b7c1237SNeil Armstrong #define HDMITX_TOP_INTR_RXSENSE_FALL BIT(7) 1023f68be7dSNeil Armstrong 103e1012141SJulien Masson /* 104e1012141SJulien Masson * Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; 1053f68be7dSNeil Armstrong * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. 1063f68be7dSNeil Armstrong * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern 1073f68be7dSNeil Armstrong * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0. 1083f68be7dSNeil Armstrong * Bit 8 RW shift_pttn_en: 1= Enable shift pattern generator; 0=Disable. 1093f68be7dSNeil Armstrong * Default 0. 1103f68be7dSNeil Armstrong * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0. 1113f68be7dSNeil Armstrong * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern; 1123f68be7dSNeil Armstrong * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0. 1133f68be7dSNeil Armstrong * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0. 1143f68be7dSNeil Armstrong */ 1153f68be7dSNeil Armstrong #define HDMITX_TOP_BIST_CNTL (0x006) 1163f68be7dSNeil Armstrong 1173f68be7dSNeil Armstrong /* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */ 1183f68be7dSNeil Armstrong /* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */ 1193f68be7dSNeil Armstrong /* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */ 1203f68be7dSNeil Armstrong #define HDMITX_TOP_SHIFT_PTTN_012 (0x007) 1213f68be7dSNeil Armstrong 1223f68be7dSNeil Armstrong /* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */ 1233f68be7dSNeil Armstrong /* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */ 1243f68be7dSNeil Armstrong /* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */ 1253f68be7dSNeil Armstrong #define HDMITX_TOP_SHIFT_PTTN_345 (0x008) 1263f68be7dSNeil Armstrong 1273f68be7dSNeil Armstrong /* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */ 1283f68be7dSNeil Armstrong /* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */ 1293f68be7dSNeil Armstrong #define HDMITX_TOP_SHIFT_PTTN_67 (0x009) 1303f68be7dSNeil Armstrong 1313f68be7dSNeil Armstrong /* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */ 1323f68be7dSNeil Armstrong /* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */ 1333f68be7dSNeil Armstrong #define HDMITX_TOP_TMDS_CLK_PTTN_01 (0x00A) 1343f68be7dSNeil Armstrong 1353f68be7dSNeil Armstrong /* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */ 1363f68be7dSNeil Armstrong /* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */ 1373f68be7dSNeil Armstrong #define HDMITX_TOP_TMDS_CLK_PTTN_23 (0x00B) 1383f68be7dSNeil Armstrong 139e1012141SJulien Masson /* 140e1012141SJulien Masson * Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, 1413f68be7dSNeil Armstrong * used when TMDS CLK rate = TMDS character rate /4. Default 0. 1423f68be7dSNeil Armstrong * Bit 0 R Reserved. Default 0. 1433f68be7dSNeil Armstrong * [ 1] shift_tmds_clk_pttn 1443f68be7dSNeil Armstrong * [ 0] load_tmds_clk_pttn 1453f68be7dSNeil Armstrong */ 1463f68be7dSNeil Armstrong #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (0x00C) 1473f68be7dSNeil Armstrong 148e1012141SJulien Masson /* 149e1012141SJulien Masson * Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM 1503f68be7dSNeil Armstrong * failure, write 1 to clear the failure flag. Default 0. 1513f68be7dSNeil Armstrong */ 1523f68be7dSNeil Armstrong #define HDMITX_TOP_REVOCMEM_STAT (0x00D) 1533f68be7dSNeil Armstrong 154e1012141SJulien Masson /* 155e1012141SJulien Masson * Bit 1 R filtered RxSense status 1563b7c1237SNeil Armstrong * Bit 0 R filtered HPD status. 1573b7c1237SNeil Armstrong */ 1583f68be7dSNeil Armstrong #define HDMITX_TOP_STAT0 (0x00E) 1593f68be7dSNeil Armstrong 1603f68be7dSNeil Armstrong #endif /* __MESON_DW_HDMI_H */ 161