Searched +full:0 +full:xff9a0000 (Results 1 – 7 of 7) sorted by relevance
6 #define VERSAL_CRL_APB_BASEADDR 0xFF5E000017 u32 iou_switch_ctrl; /* 0x114 */19 u32 timestamp_ref_ctrl; /* 0x14c */23 u32 rst_timestamp; /* 0x348 */28 #define VERSAL_IOU_SCNTR_SECURE 0xFF14000033 u32 counter_control_register; /* 0x0 */35 u32 base_frequency_id_register; /* 0x20 */40 #define VERSAL_TCM_BASE_ADDR 0xFFE0000041 #define VERSAL_TCM_SIZE 0x4000043 #define VERSAL_RPU_BASEADDR 0xFF9A0000[all …]
89 reg = <0xff9a0000 0x800>;
10 #define ARASAN_NAND_BASEADDR 0xFF10000012 #define ZYNQMP_TCM_BASE_ADDR 0xFFE0000013 #define ZYNQMP_TCM_SIZE 0x4000015 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E000016 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x100000017 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 020 #define PS_MODE0 BIT(0)31 #define RESET_REASON_EXTERNAL BIT(0)35 u32 cpu_r5_ctrl; /* 0x90 */37 u32 timestamp_ref_ctrl; /* 0x128 */[all …]
53 #size-cells = <0>;60 reg = <0x500>;85 reg = <0x501>;91 reg = <0x502>;97 reg = <0x503>;111 reg = <0xff250000 0x4000>;122 reg = <0xff600000 0x4000>;123 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,134 reg = <0xffb20000 0x4000>;135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,[all …]
43 #size-cells = <0>;71 cpu_l0: cpu@0 {74 reg = <0x0 0x0>;83 reg = <0x0 0x1>;91 reg = <0x0 0x2>;99 reg = <0x0 0x3>;107 reg = <0x0 0x100>;116 reg = <0x0 0x101>;139 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,140 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,[all …]
53 #size-cells = <0>;60 reg = <0x500>;71 reg = <0x501>;82 reg = <0x502>;93 reg = <0x503>;103 cpu_opp_table: opp-table-0 {163 * The rk3288 cannot use the memory area above 0xfe000000173 reg = <0x0 0xfe000000 0x0 0x1000000>;181 #clock-cells = <0>;197 reg = <0x0 0xff810000 0x0 0x20>;[all …]
41 #size-cells = <0>;69 cpu_l0: cpu@0 {72 reg = <0x0 0x0>;84 reg = <0x0 0x1>;96 reg = <0x0 0x2>;108 reg = <0x0 0x3>;120 reg = <0x0 0x100>;138 reg = <0x0 0x101>;159 arm,psci-suspend-param = <0x0010000>;168 arm,psci-suspend-param = <0x1010000>;[all …]