Lines Matching +full:0 +full:xff9a0000

6 #define VERSAL_CRL_APB_BASEADDR	0xFF5E0000
17 	u32 iou_switch_ctrl; /* 0x114 */
19 	u32 timestamp_ref_ctrl; /* 0x14c */
23 	u32 rst_timestamp; /* 0x348 */
28 #define VERSAL_IOU_SCNTR_SECURE	0xFF140000
33 	u32 counter_control_register; /* 0x0 */
35 	u32 base_frequency_id_register; /* 0x20 */
40 #define VERSAL_TCM_BASE_ADDR	0xFFE00000
41 #define VERSAL_TCM_SIZE		0x40000
43 #define VERSAL_RPU_BASEADDR	0xFF9A0000
48 	u32 rpu0_cfg; /* 0x100 */
50 	u32 rpu1_cfg; /* 0x200 */