arm/dts/rk3288.dtsi

53 		#size-cells = <0>;
60 			reg = <0x500>;
85 			reg = <0x501>;
91 			reg = <0x502>;
97 			reg = <0x503>;
111 			reg = <0xff250000 0x4000>;
122 			reg = <0xff600000 0x4000>;
123 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
134 			reg = <0xffb20000 0x4000>;
135 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
147 		#clock-cells = <0>;
172 		fifo-depth = <0x100>;
174 		reg = <0xff0c0000 0x4000>;
184 		fifo-depth = <0x100>;
186 		reg = <0xff0d0000 0x4000>;
196 		fifo-depth = <0x100>;
198 		reg = <0xff0e0000 0x4000>;
208 		fifo-depth = <0x100>;
210 		reg = <0xff0f0000 0x4000>;
216 		reg = <0xff100000 0x100>;
232 		pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
233 		reg = <0xff110000 0x1000>;
235 		#size-cells = <0>;
247 		pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
248 		reg = <0xff120000 0x1000>;
250 		#size-cells = <0>;
262 		pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
263 		reg = <0xff130000 0x1000>;
265 		#size-cells = <0>;
271 		reg = <0xff140000 0x1000>;
274 		#size-cells = <0>;
278 		pinctrl-0 = <&i2c1_xfer>;
284 		reg = <0xff150000 0x1000>;
287 		#size-cells = <0>;
291 		pinctrl-0 = <&i2c3_xfer>;
297 		reg = <0xff160000 0x1000>;
300 		#size-cells = <0>;
304 		pinctrl-0 = <&i2c4_xfer>;
310 		reg = <0xff170000 0x1000>;
313 		#size-cells = <0>;
317 		pinctrl-0 = <&i2c5_xfer>;
322 		reg = <0xff180000 0x100>;
330 		pinctrl-0 = <&uart0_xfer>;
336 		reg = <0xff190000 0x100>;
344 		pinctrl-0 = <&uart1_xfer>;
350 		reg = <0xff690000 0x100>;
358 		pinctrl-0 = <&uart2_xfer>;
363 		reg = <0xff1b0000 0x100>;
371 		pinctrl-0 = <&uart3_xfer>;
377 		reg = <0xff1c0000 0x100>;
385 		pinctrl-0 = <&uart4_xfer>;
394 		reg = <0xff280000 0x100>;
401 		pinctrl-0 = <&otp_out>;
409 		reg = <0xff290000 0x10000>;
425 		reg = <0xff500000 0x100>;
439 		reg = <0xff540000 0x40000>;
451 		reg = <0xff580000 0x40000>;
463 		reg = <0xff5c0000 0x100>;
478 		reg = <0xff610000 0x3fc
479 		       0xff620000 0x294
480 		       0xff630000 0x3fc
481 		       0xff640000 0x294>;
493 		reg = <0xff650000 0x1000>;
496 		#size-cells = <0>;
500 		pinctrl-0 = <&i2c0_xfer>;
506 		reg = <0xff660000 0x1000>;
509 		#size-cells = <0>;
513 		pinctrl-0 = <&i2c2_xfer>;
519 		reg = <0xff680000 0x10>;
522 		pinctrl-0 = <&pwm0_pin>;
531 		reg = <0xff680010 0x10>;
534 		pinctrl-0 = <&pwm1_pin>;
543 		reg = <0xff680020 0x10>;
546 		pinctrl-0 = <&pwm2_pin>;
555 		reg = <0xff680030 0x10>;
558 		pinctrl-0 = <&pwm3_pin>;
567 		reg = <0xff700000 0x18000>;
570 		ranges = <0 0xff700000 0x18000>;
571 		smp-sram@0 {
573 			reg = <0x00 0x10>;
577 			reg = <0x1000 0x4000>;
583 		reg = <0xff720000 0x1000>;
589 		reg = <0xff730000 0x100>;
595 		reg = <0xff740000 0x1000>;
600 		reg = <0xff760000 0x1000>;
620 		reg = <0xff770000 0x1000>;
625 		reg = <0xff800000 0x100>;
633 		reg = <0xff8b0000 0x10000>;
634 		#sound-dai-cells = <0>;
641 		pinctrl-0 = <&spdif_tx>;
648 		reg = <0xff890000 0x10000>;
651 		#size-cells = <0>;
653 		dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
658 		pinctrl-0 = <&i2s0_bus>;
665 		reg = <0xff930000 0x19c>;
676 			#size-cells = <0>;
677 			vopb_out_edp: endpoint@0 {
678 				reg = <0>;
699 		reg = <0xff930300 0x100>;
703 		#iommu-cells = <0>;
709 		reg = <0xff940000 0x19c>;
721 			#size-cells = <0>;
722 			vopl_out_edp: endpoint@0 {
723 				reg = <0>;
744 		reg = <0xff940300 0x100>;
748 		#iommu-cells = <0>;
754 		reg = <0xff970000 0x4000>;
766 				#size-cells = <0>;
767 				edp_in_vopb: endpoint@0 {
768 					reg = <0>;
781 		reg = <0xff980000 0x20000>;
792 				#size-cells = <0>;
793 				hdmi_in_vopb: endpoint@0 {
794 					reg = <0>;
807 		reg = <0xff96c000 0x4000>;
811 		pinctrl-0 = <&lcdc0_ctl>;
816 			#size-cells = <0>;
817 			lvds_in: port@0 {
818 				reg = <0>;
820 				#size-cells = <0>;
821 				lvds_in_vopb: endpoint@0 {
822 					reg = <0>;
835 		reg = <0xff960000 0x4000>;
839 		pinctrl-0 = <&lcdc0_ctl>;*/
842 		#size-cells = <0>;
848 				#size-cells = <0>;
849 				mipi_in_vopb: endpoint@0 {
850 					reg = <0>;
869 		reg = <0xff9a0000 0x800>;
881 		reg = <0xff9a0800 0x100>;
885 		#iommu-cells = <0>;
893 		reg = <0xffa30000 0x10000>;
916 		reg = <0xffac0000 0x2000>;
921 		reg = <0xffb40000 0x10000>;
929 		#address-cells = <0>;
931 		reg = <0xffc01000 0x1000>,
932 		      <0xffc02000 0x1000>,
933 		      <0xffc04000 0x2000>,
934 		      <0xffc06000 0x2000>;
935 		interrupts = <GIC_PPI 9 0xf04>;
946 		#size-cells = <0>;
950 			#phy-cells = <0>;
951 			reg = <0x320>;
957 			#phy-cells = <0>;
958 			reg = <0x334>;
964 			#phy-cells = <0>;
965 			reg = <0x348>;
981 			reg =	<0xff750000 0x100>;
994 			reg = <0xff780000 0x100>;
1007 			reg = <0xff790000 0x100>;
1020 			reg = <0xff7a0000 0x100>;
1033 			reg = <0xff7b0000 0x100>;
1046 			reg = <0xff7c0000 0x100>;
1059 			reg = <0xff7d0000 0x100>;
1072 			reg = <0xff7e0000 0x100>;
1085 			reg = <0xff7f0000 0x100>;
1115 				rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1119 				rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1123 				rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1127 				rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1133 				rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1134 						<0 16 RK_FUNC_1 &pcfg_pull_none>;
1175 				rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1314 				rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1318 				rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1325 				rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1456 				rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1462 				rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1494 						<4 0 3 &pcfg_pull_none>,
1508 						<4 0 3 &pcfg_pull_none>,
1529 		#size-cells = <0>;